Sundance SMT943 - Manual (Page 26)

User Manual SMT943 Page 26 of 54 Last Edited: 23/08/2011 17:24:00
1 1
Setting Bit 8 Description Output Divider Enable DAC cha&b clk2
0 0 Divider disabled.
1 1 Divider enabled.
Setting Bit 9 Description PECL3HISWING PECL output voltage swing (DAC cha&b clk2)
0 0 Normal Operation.
1 1 High PECL output voltage.
Setting Bit 15:10 Description Output3 (DAC cha&b clk2) mode
0 0 LVPECL only: ‘100000’.
CLOCK Register 8 0x18.
Clock Register 8 0x18
Byte Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
1 Coarse Phase Adjustment[5:0] (External Clock) Reserved HOLD_ON_LOR
Default ‘000000’ ‘0’ ‘0’
0 Reserved Reserved
Default ‘0000’ ‘0011’
Reset Register 8 0x18
Setting Bit 8 Description HOLD_ON_LOR
0 0 Normal mode of operation
1 1 Charge pump in tri-state mode
Setting Bit 15:10 Description Coarse Phase Adjustment[5:0] External Clock
0 0
1 1
CLOCK Register 9 0x19.
Clock Register 9 0x19
Byte Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
1 Output0 (External Clock) Mode PECL4HISWING Output
Divider
Enable
Default ‘100000’ ‘0’ ‘0’
0 Output Divider Ratio External Clock Coarse Phase
Adjustment[6]
Default ‘0000000’ ‘0’