Sundance SMT943 - Manual (Page 32)

User Manual SMT943 Page 32 of 54 Last Edited: 23/08/2011 17:24:00
CLOCK Register 15 0x25.
Clock Register 15 0x25
Byte Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
1 VCXO Divider N[13:6]
Default ‘000000’
0 VCXO Divider N[5:0] Reference Divider
M[13:12]
Default ‘000000’ ‘00’
Reset Register 15 0x25
Setting Bit 1:0 Description Reference Divider M[13:12]
0
1
Setting Bit 15:2 Description VCXO Divider N[13:0]
0
1
CLOCK Register 16 0x26.
Clock Register 16 0x26
Byte Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
1 FB_COUNTER FB_INCLK_I
NV
Default ‘0000000’ ‘0’
0 FB_CML_SE
L
FB_DIS SEC_DIV2 PRI_DIV2 Reserved
Default ‘0’ ‘0’ ‘0’ ‘0’ ‘1011’
Reset Register 16 0x26
Setting Bit 4 Description PRI_DIV2
0 ‘0’ Primary reference divider disabled
1 ‘1’ Primary reference divider enabled
Setting Bit 5 Description SEC_DIV2
0 ‘0’ Secondary reference divider disabled
1 ‘1’ Secondary reference divider enabled
Setting Bit 6 Description FB_DIS
0 ‘0’ FB Divider is active
1 ‘1’ FB Divider is disabled
Setting Bit 7 Description FB_CML_SEL
0 ‘0’ FB is CMOS type
1 ‘1’ FB is CML type
Setting Bit 8 Description FB_INCLK_INV