BECKHOFF EtherCAT IP Core for Altera FPGAs v3.0.10 User Manual
BECKHOFF Equipment
Table of contents
Document Outline
- Section III – Hardware Description
- 1 Overview
- 2 Features and Registers
- 3 IP Core Installation
- 4 IP Core Usage
- 5 IP Core Configuration
- 6 Example Designs
- 7 FPGA Resource Consumption
- 8 IP Core Signals
- 9 Ethernet Interface
- 10 PDI Description
- 10.1 Digital I/O Interface
- 10.2 SPI Slave Interface
- 10.3 Asynchronous 8/16 bit µController Interface
- 10.4 Avalon Slave Interface
- 10.5 AXI3 On-Chip Bus
- 11 Distributed Clocks SYNC/LATCH Signals
- 12 SII EEPROM Interface (I²C)
- 13 Electrical Specifications
- 14 Synthesis Constraints
- 15 Appendix