5 timing specifications, Timing specifications, Table 58: avalon timing characteristics – BECKHOFF EtherCAT IP Core for Altera FPGAs v3.0.10 User Manual
Page 127

PDI Description
Slave Controller
– IP Core for Altera FPGAs
III-115
10.4.5 Timing specifications
Table 58: Avalon timing characteristics
Parameter
Min
Max
Comment
PRELIMINARY TIMING
D
8, 16, 32, or 64
Avalon data bus width (in Bits)
=PDI_EXT_BUS_WIDTH
N
1
31
Avalon bus clock factor (if bus
clock is a multiple of 25 MHz)
t
Clk
x
10
40 ns
Avalon bus clock period
(CLK_PDI_EXT)
t
Read
a) 4 * t
CLK
+D * 5 ns
+x
b) 6.5 * t
CLK
+D * 5 ns
+100 ns
+x
a) 3 * t
CLK
+D * 5 ns
+40 ns
+x
b) 6.5 * t
CLK
+D * 5 ns
+180 ns
+x
Aligned read access time
a) synchronous (N=1-31)
b) asynchronous
t
Write
a) 3 * t
CLK
b) 5.5 * t
CLK
+100 ns
+x
a) D * 5 ns
b) D * 5 ns
+140 ns
+x
Aligned write access time
a) synchronous (N=1-31)
b) asynchronous
10
EtherCAT IP Core: time depends on synthesis results
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