Sp i m od e 1 /3 sp i m od e 0 /2 – BECKHOFF EtherCAT IP Core for Altera FPGAs v3.0.10 User Manual
Page 113

PDI Description
Slave Controller
– IP Core for Altera FPGAs
III-101
C
0
0
S
P
I_
S
E
L
S
P
I_
C
L
K
m
o
d
e
0
S
P
I_
C
L
K
m
o
d
e
2
S
P
I_
C
L
K
m
o
d
e
3
S
P
I_
C
L
K
m
o
d
e
1
S
P
I_
D
O
(
M
IS
O
)
la
te
s
a
m
p
le
,
m
o
d
e
1
/3
S
P
I_
D
O
(
M
IS
O
)
la
te
s
a
m
p
le
,
m
o
d
e
0
/2
S
P
I_
D
O
(
M
IS
O
)
n
o
rm
a
l
s
a
m
p
le
,
m
o
d
e
1
/3
S
P
I_
D
O
(
M
IS
O
)
n
o
rm
a
l
s
a
m
p
le
,
m
o
d
e
0
/2
A
1
2
A
1
1
A
1
0
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
S
P
I_
D
I
(M
O
S
I)
I0
7
I0
6
I0
5
I0
4
I0
3
I0
2
I0
1
I0
0
I1
7
I1
6
I1
5
I1
4
I1
3
I1
2
I1
1
S
ta
tu
s
I0
6
I0
5
I0
4
I0
3
I0
2
I0
1
I0
0
I1
7
I1
6
I1
5
I1
4
I1
3
I1
2
I1
1
I0
7
I0
6
I0
5
I0
4
I0
3
I0
2
I0
1
I0
0
I1
7
I1
6
I1
5
I1
4
I1
3
I1
2
I1
1
I0
7
S
ta
tu
s
I0
6
I0
5
I0
4
I0
3
I0
2
I0
1
I1
7
I1
6
I1
5
I1
4
I1
3
I1
2
I1
1
A
1
2
A
1
1
A
1
0
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
S
P
I_
D
I
(M
O
S
I)
D
0
7
D
0
6
D
0
5
D
0
4
D
0
3
D
0
2
D
0
1
D
0
6
D
0
5
D
0
4
D
0
3
D
0
2
D
0
1
t
S
E
L
_
to
_
C
L
K
t
C
L
K
t
C
L
K
t
S
E
L
_
to
_
D
O
_
v
a
lid
t
S
E
L
_
to
_
C
L
K
t
C
L
K
_
to
_
S
E
L
t
C
L
K
_
to
_
S
E
L
R
e
a
d
T
e
rm
in
a
ti
o
n
b
y
te
D
0
0
t
S
E
L
_
to
_
D
O
_
in
v
a
lid
SP
I m
od
e 1
/3
SP
I m
od
e 0
/2
A
d
d
re
s
s
/C
o
m
m
a
n
d
B
y
te
0
A
d
d
re
s
s
/C
o
m
m
a
n
d
B
y
te
1
W
a
it
S
ta
te
b
y
te
D
a
ta
B
y
te
0
C
0
2
C
0
1
C
0
2
C
0
1
I1
0
D
0
7
W
a
it
S
ta
te
b
y
te
D
0
7
D
0
6
D
0
5
D
0
4
D
0
3
D
0
2
D
0
1
D
0
6
D
0
5
D
0
4
D
0
3
D
0
2
D
0
1
D
0
0
D
0
0
I1
0
I1
0
D
0
7
C
0
0
R
e
a
d
T
e
rm
in
a
ti
o
n
b
y
te
W
a
it
S
ta
te
b
y
te
I0
0
I1
0
D
0
0
I0
7
S
ta
tu
s
Fi
gu
re
42
: SPI
re
a
d
a
c
c
e
s
s
(
2
b
y
te
a
dd
res
s
in
g,
1
b
y
te
re
a
d
da
ta
) with
W
a
it
Sta
te
by
te