BECKHOFF EtherCAT IP Core for Altera FPGAs v3.0.10 - Manual (Page 6)

CONTENTS
III-VI Slave Controller – IP Core for Altera FPGAs
8.6.5 Avalon On-Chip Bus 72
8.6.6 AXI3 On-Chip Bus 73
9 Ethernet Interface 74
9.1 PHY Management interface 74
9.1.1 PHY Management Interface Signals 74
9.1.2 PHY Address Configuration 74
9.1.3 Separate external MII management interfaces 75
9.1.4 MII management timing specifications 75
9.2 MII Interface 76
9.2.1 MII Interface Signals 77
9.2.2 TX Shift Compensation 78
9.2.3 MII Timing specifications 79
9.2.4 MII example schematic 80
9.3 RMII Interface 81
9.3.1 RMII Interface Signals 81
9.3.2 RMII example schematic 82
9.4 RGMII Interface 83
9.4.1 RGMII Interface Signals 83
9.4.2 RGMII example schematic 85
9.4.3 RGMII RX timing options 85
9.4.4 RGMII TX timing options 85
10 PDI Description 87
10.1 Digital I/O Interface 88
10.1.1 Interface 88
10.1.2 Configuration 89
10.1.3 Digital Inputs 89
10.1.4 Digital Outputs 89
10.1.5 Output Enable 90
10.1.6 SyncManager Watchdog 90
10.1.7 SOF 91
10.1.8 OUTVALID 91
10.1.9 Timing specifications 91
10.2 SPI Slave Interface 94
10.2.1 Interface 94
10.2.2 Configuration 94
10.2.3 SPI access 95
10.2.4 Address modes 95
10.2.5 Commands 96
10.2.6 Interrupt request register (AL Event register) 96
10.2.7 Write access 96
10.2.8 Read access 96