BECKHOFF EtherCAT IP Core for Altera FPGAs v3.0.10 - Manual (Page 70)

FPGA Resource Consumption
III-58 Slave Controller – IP Core for Altera FPGAs
The EtherCAT IP core resource consumption figures for typical EtherCAT devices are based on
EtherCAT IP Core for Altera FPGAs Version 3.0.2, Altera Quartus II 12.1 SP1, and Altera Cyclone IV
devices.
Table 18: EtherCAT IP Core configuration for typical EtherCAT Devices
EtherCAT Device SM FMMU
DPRAM
[kByte]
PDI DC
Logic
Elements
IO 2 2 1 32 Bit Digital I/O - 8,800
Frequency Inverter 4 4 1 SPI - 13,900
Encoder 4 4 1 SPI 32 18,600
Fieldbus Gateway 4 4 4 16 Bit µC - 13,800
Servo Drive 4 4 4 16 Bit µC 32 18,200
NOTE: Register preset medium and large including MII Management Interface. All devices have 2 MII ports, DC is
32 bit wide, and typical features are selected.