BECKHOFF EtherCAT IP Core for Altera FPGAs v3.0.10 - Manual (Page 56)

IP Core Configuration
III-44 Slave Controller – IP Core for Altera FPGAs
Output Mode
Defines the trigger signal for data output.

Output at EOF (End of Frame)
The outputs will be set if the frame containing the data is received complete and error free.

Output at Dist-Sync0
Outputs will be set with Sync0 signal if distributed clocks are enabled.

Output at Dist-Sync1
Outputs will be set with Sync1 signal if distributed clocks are enabled.