BECKHOFF EtherCAT IP Core for Altera FPGAs v3.0.10 - Manual (Page 9)

TABLES
Slave Controller – IP Core for Altera FPGAs III-IX
Table 61: Distributed Clocks signals ................................................................................................... 122
Table 62: DC SYNC/LATCH timing characteristics IP Core ............................................................... 122
Table 63: I²C EEPROM signals ........................................................................................................... 123
Table 64: EEPROM timing characteristics IP Core ............................................................................. 123
Table 65: AC Characteristics ............................................................................................................... 124
Table 66: Forwarding Delays ............................................................................................................... 124
Table 67: EtherCAT IP Core constraints ............................................................................................. 125