BECKHOFF EtherCAT IP Core for Altera FPGAs v3.0.10 - Manual (Page 50)

IP Core Configuration
III-38 Slave Controller – IP Core for Altera FPGAs
Distributed Clocks enabled
The Distributed Clocks feature comprises synchronized distributed clocks, receive times, SyncSignal
generation, and LatchSignal time stamping.
DC SyncSignals
Select the number of SyncSignals.
DC LatchSignals
Select the number of LatchSignals.
Distributed Clocks Width
The width of the Distributed Clocks can be selected to be either 32 bit or 64 bit. DC with 64 bit require
more FPGA resources. DC with 32 bit and DC with 64 bit are interoperable.
Cyclic pulse length
Determines the length of SyncSignal output (register 0x0982:0x0983).
Mapping to global IRQ
Sync0 and Sync1 can additionally be mapped internally to the global IRQ. This might be a good
solution if a microcontroller interface is short on IRQs. However, the sync signals will remain available
on Sync0 and Sync1 outputs.