BECKHOFF EtherCAT IP Core for Altera FPGAs v3.0.10 - Manual (Page 4)

CONTENTS
III-IV Slave Controller – IP Core for Altera FPGAs
CONTENTS
1 Overview 1
1.1 Frame processing order 2
1.2 Scope of this document 3
1.3 Scope of Delivery 3
1.4 Target FPGAs 4
1.5 Designflow requirements 4
1.6 Tested FPGA/Designflow combinations 5
1.7 Release Notes 6
1.7.1 Major differences between V2.4.x and V3.0.x 12
1.7.2 Reading IP Core version from device 12
1.8 Design flow 13
1.9 OpenCore Plus Evaluation 14
1.10 Simulation 15
2 Features and Registers 16
2.1 Features 16
2.2 Registers 19
2.3 Extended ESC Features in User RAM 22
3 IP Core Installation 26
3.1 Installation on Windows PCs 26
3.1.1 System Requirements 26
3.1.2 Installation 26
3.2 Installation on Linux PCs 27
3.2.1 System Requirements 27
3.2.2 Installation 27
3.3 Files located in the lib folder 27
3.4 License File 28
3.5 IP Core Vendor ID package 29
3.6 Integrating the EtherCAT IP Core into the Altera Designflow 30
3.6.1 Software Templates for example designs with NIOS processor 30
3.7 EtherCAT Slave Information (ESI) / XML device description for example designs 30
4 IP Core Usage 31
4.1 IP Catalog 31
4.2 Qsys 31
5 IP Core Configuration 32
5.1 Documentation 33
5.2 Parameters 34
5.2.1 Product ID tab 34
5.2.2 Physical Layer tab 35
5.2.3 Internal Functions tab 37