BECKHOFF EtherCAT IP Core for Altera FPGAs v3.0.10 - Manual (Page 23)

Overview
Slave Controller – IP Core for Altera FPGAs III-11
Version Release notes
3.0.10
(1/2015)
The EL9800/FB1122 example designs have been removed because these evaluation
boards are no longer available.
Enhancements:

For EEPROM Emulation, the CRC error bit 0x0502[11] can be written via PDI to
indicate CRC errors during a reload command.
Restrictions of previous versions which are removed in this version:

The last 4 Kbyte Process Data RAM (0xF000:0xFFFF) can be used in the 60
Kbyte RAM configuration.

The AXI PDI does not write to wrong bytes if the write data is valid before the
address.

The AXI PDI does not read additional bytes after the intended bytes.

The AXI PDI does not write to byte lanes without byte enable.