BECKHOFF EtherCAT IP Core for Altera FPGAs v3.0.10 - Manual (Page 129)

PDI Description
Slave Controller – IP Core for Altera FPGAs III-117
10.5 AXI3 On-Chip Bus
10.5.1 Interface
The AXI3 Slave PDI is selected during the IP Core configuration. The signals of the AXI3 interface
are
11 :
EtherCAT
IP core
CLK_PDI_EXT
Read address
channel
Read data
channel
Write address
channel
Write data
channel
Write response
channel
IRQ_MAIN
IRQ_DC_SYNC0/1
Figure 57: AXI3 signals
Table 59: AXI3 signals
Signal
Directio
n
Description Channel
Signal
polarity
CLK_PDI_EXT IN AXI Bus clock
PDI_AXI_AWID
[PDI_BUS_ID_WIDTH-1:0] IN Write address ID WR addr.
PDI_AXI_AWADDR[15:0] IN Write address WR addr.
PDI_AXI3_AWLEN[3:0] IN Write length WR addr.
PDI_AXI_AWSIZE[2:0] IN Write size WR addr.
PDI_AXI_AWBURST[1:0] IN Write burst type WR addr.
PDI_AXI3_AWLOCK IN Write lock WR addr.
PDI_AXI_AWCACHE[3:0] IN Write cache type WR addr.
PDI_AXI_AWPROT[2:0] IN Write protection type WR addr.
PDI_AXI_AWVALID IN Write address valid WR addr. act. high
PDI_AXI_AWREADY OUT Write address ready WR addr. act. high
PDI_AXI_WID
[PDI_BUS_ID_WIDTH-1:0] IN Write data ID WR data
PDI_AXI_WDATA
[PDI_EXT_BUS_WIDTH-1:0] IN Write data WR data
PDI_AXI_WSTRB
[PDI_EXT_BUS_WIDTH/8-1:0] IN Write data byte enable WR data act. high
11 The prefix `PDI_AXI_` or is added to the AXI3 interface signals for the IP Core interface.