BECKHOFF EtherCAT IP Core for Altera FPGAs v3.0.10 - Manual (Page 60)

IP Core Configuration
III-48 Slave Controller – IP Core for Altera FPGAs
5.2.5.6 AXI3 Configuration
The AXI3 PDI connects the IP Core with an AXI Master. The AXI3 PDI uses memory
addressing/dynamic bus sizing.
Figure 19: Register PDI – AXI3 Interface Configuration
Device emulation
Enable Device emulation (0x0141[0]=1). This feature should be disabled in most use cases.
On-chip Bus CLK
This is the clock period of the AXI bus clock for communication between ESC and the AXI master.
This configuration option is not available if the clock period can be derived from the Qsys clock
connections.
On-Chip Bus CLK is asynchronous to CLK25 core clock
Enable if the On-chip BUS CLK is asynchronous to CLK25. Additional synchronization stages are
added in this case.
External data bus width
Select the AXI data bus width (8/16/32/64 bit) of the AXI slave interface.
ID width
Width of the access ID signals.