BECKHOFF EtherCAT IP Core for Altera FPGAs v3.0.10 - Manual (Page 66)

Example Designs
III-54 Slave Controller – IP Core for Altera FPGAs
6.3 Altera Cyclone IV DE2-115 with NIOS and MII
6.3.1 Configuration and resource consumption
Table 15: Resource consumption NIOS example design DE2-115 MII
Configuration Resources EP4CE115
Physical layer 2x MII,
TX Shift, MIIM, Link state
and PHY configuration
through MI Les 19,062 17 %
Internal Function 3x FMMU
4x SyncManager
1 KB RAM Registers 9,039 8 %
Distributed clocks 32 bit,
2x Sync, 2x Latch M9K 264 61 %
Feature details AL Status Code register,
Extended Watchdog,
AL Event Mask register,
Watchdog counter, EPU
and PDI Error counter,
Lost Link Counter,
RUN_LED,
LED Test PLLs 1 25 %
PDI Avalon
32 bit Multiplier
elements 0 0 %
6.3.2 Functionality
Configure ETHERNET0 and ETHERNET1 for MII mode by setting jumpers JP1 and JP2 to 2-3.
Master is connected to Port ETHERNET0 of DE2-115 (left side, next to VGA). Port ETHERNET1 (right
side) can be used to connect other EtherCAT slaves.
The NIOS demo application performs the following tasks:

Accept any EtherCAT Slave State request (copying AL Control to AL Status register)

Display EtherCAT IP Core version and slave state on LCD

RUN LED is LEDG8

Link/Activity LEDs are LEDG6 and LEDG7

LEDG0 – LEDG5 are showing a running light if the slave is in OPERATIONAL mode

Digital input data from the switches SW0-SW17 is available in the Process Data RAM
(0x1000:0x1003).

Digital input data from the push buttons KEY0-KEY3 is available in the Process Data RAM
(0x1004).

Digital output data from Digital Output register (0x1100:0x1103) is visualized with LEDR0-LEDR17

Digital output data from Digital Output register (0x1104:0x1107) is visualized with the 7-segment
LED displays
The NIOS demo application is not suitable for production, it cannot be certified. Use the EtherCAT
Slave Stack Code (SSC, available from the ETG) for products.