Altera Arria V GX FPGA Development Board - Manual (Page 76)

2–66 Chapter 2: Board Components
Memory
Arria V GX FPGA Development Board November 2013 Altera Corporation
Reference Manual
L7 DDR3B_A10 C32 1.5-V SSTL Class I Address bus
R7 DDR3B_A11 D32 1.5-V SSTL Class I Address bus
N7 DDR3B_A12 N31 1.5-V SSTL Class I Address bus
T3 DDR3B_A13 P31 1.5-V SSTL Class I Address bus
M2 DDR3B_BA0 M32 1.5-V SSTL Class I Bank address bus
N8 DDR3B_BA1 N32 1.5-V SSTL Class I Bank address bus
M3 DDR3B_BA2 J34 1.5-V SSTL Class I Bank address bus
K3 DDR3B_CASN L33 1.5-V SSTL Class I Row address select
K9 DDR3B_CKE E31 1.5-V SSTL Class I Column address select
K7 DDR3B_CLK_N C30 1.5-V SSTL Class I Differential output clock
J7 DDR3B_CLK_P B30 1.5-V SSTL Class I Differential output clock
L2 DDR3B_CSN L34 1.5-V SSTL Class I Chip select
K1 DDR3B_ODT L31 1.5-V SSTL Class I On-die termination enable
J3 DDR3B_RASN K34 1.5-V SSTL Class I Row address select
T2 DDR3B_RESETN G30 1.5-V SSTL Class I Reset
L3 DDR3B_WEN M33 1.5-V SSTL Class I Write enable
DDR3C (U19)
E7 DDR3C_DM0 M21 1.5-V SSTL Class I Write mask byte lane
D3 DDR3C_DM1 B22 1.5-V SSTL Class I Write mask byte lane
E3 DDR3C_DQ0 D20 1.5-V SSTL Class I Data bus byte lane
F7 DDR3C_DQ1 H21 1.5-V SSTL Class I Data bus byte lane
F2 DDR3C_DQ2 D21 1.5-V SSTL Class I Data bus byte lane
F8 DDR3C_DQ3 J21 1.5-V SSTL Class I Data bus byte lane
H3 DDR3C_DQ4 A21 1.5-V SSTL Class I Data bus byte lane
H8 DDR3C_DQ5 G21 1.5-V SSTL Class I Data bus byte lane
G2 DDR3C_DQ6 A22 1.5-V SSTL Class I Data bus byte lane
H7 DDR3C_DQ7 C20 1.5-V SSTL Class I Data bus byte lane
D7 DDR3C_DQ8 A23 1.5-V SSTL Class I Data bus byte lane
C3 DDR3C_DQ9 E22 1.5-V SSTL Class I Data bus byte lane
C8 DDR3C_DQ10 L22 1.5-V SSTL Class I Data bus byte lane
C2 DDR3C_DQ11 C22 1.5-V SSTL Class I Data bus byte lane
A7 DDR3C_DQ12 N22 1.5-V SSTL Class I Data bus byte lane
A2 DDR3C_DQ13 F22 1.5-V SSTL Class I Data bus byte lane
B8 DDR3C_DQ14 P22 1.5-V SSTL Class I Data bus byte lane
A3 DDR3C_DQ15 J22 1.5-V SSTL Class I Data bus byte lane
G3 DDR3C_DQS_N0 B21 1.5-V SSTL Class I Data strobe N byte lane
B7 DDR3C_DQS_N1 D23 1.5-V SSTL Class I Data strobe N byte lane
F3 DDR3C_DQS_P0 A20 1.5-V SSTL Class I Data strobe P byte lane
C7 DDR3C_DQS_P1 C23 1.5-V SSTL Class I Data strobe P byte lane
Table 2–56. DDR3 x64 Devices Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 3)
Board Reference
Schematic
Signal Name
Arria V GX FPGA
Pin Number
I/O Standard Description