Altera Arria V GX FPGA Development Board User Manual
Page 58
2–48
Chapter 2: Board Components
Components and Interfaces
Arria V GX FPGA Development Board
November 2013
Altera Corporation
Reference Manual
90
HSMB_RX_D_P7
AP29
LVDS or 2.5-V LVDS RX bit 7 or CMOS bit 33
91
HSMB_TX_D_N7
AL31
LVDS or 2.5-V LVDS TX bit 7n or CMOS bit 34
92
HSMB_RX_D_N7
AN29
LVDS or 2.5-V LVDS RX bit 7n or CMOS bit 35
95
HSMB_CLK_OUT_P1
AM34
LVDS or 2.5-V LVDS or CMOS clock out 1 or CMOS bit 36
96
HSMB_CLK_IN_P1
AM33
LVDS or 2.5-V LVDS or CMOS clock in 1 or CMOS bit 37
97
HSMB_CLK_OUT_N1
AL34
LVDS or 2.5-V LVDS or CMOS clock out 1 or CMOS bit 38
98
HSMB_CLK_IN_N1
AL33
LVDS or 2.5-V LVDS or CMOS clock in 1 or CMOS bit 39
101
HSMB_TX_D_P8
AN27
LVDS or 2.5-V LVDS TX bit 8 or CMOS bit 40
102
HSMB_RX_D_P8
AU29
LVDS or 2.5-V LVDS RX bit 8 or CMOS bit 41
103
HSMB_TX_D_N8
AM27
LVDS or 2.5-V LVDS TX bit 8n or CMOS bit 42
104
HSMB_RX_D_N8
AT29
LVDS or 2.5-V LVDS RX bit 8n or CMOS bit 43
107
HSMB_TX_D_P9
AP30
LVDS or 2.5-V LVDS TX bit 9 or CMOS bit 44
108
HSMB_RX_D_P9
AW31
LVDS or 2.5-V LVDS RX bit 9 or CMOS bit 45
109
HSMB_TX_D_N9
AN30
LVDS or 2.5-V LVDS TX bit 9n or CMOS bit 46
110
HSMB_RX_D_N9
AW30
LVDS or 2.5-V LVDS RX bit 9n or CMOS bit 47
113
HSMB_TX_D_P10
AR28
LVDS or 2.5-V LVDS TX bit 10 or CMOS bit 48
114
HSMB_RX_D_P10
AW28
LVDS or 2.5-V LVDS RX bit 10 or CMOS bit 49
115
HSMB_TX_D_N10
AP28
LVDS or 2.5-V LVDS TX bit 10n or CMOS bit 50
116
HSMB_RX_D_N10
AW29
LVDS or 2.5-V LVDS RX bit 10n or CMOS bit 51
119
HSMB_TX_D_P11
AV30
LVDS or 2.5-V LVDS TX bit 11 or CMOS bit 52
120
HSMB_RX_D_P11
AU27
LVDS or 2.5-V LVDS RX bit 11 or CMOS bit 53
121
HSMB_TX_D_N11
AU30
LVDS or 2.5-V LVDS TX bit 11n or CMOS bit 54
122
HSMB_RX_D_N11
AT27
LVDS or 2.5-V LVDS RX bit 11n or CMOS bit 55
125
HSMB_TX_D_P12
AV31
LVDS or 2.5-V LVDS TX bit 12 or CMOS bit 56
126
HSMB_RX_D_P12
AW27
LVDS or 2.5-V LVDS RX bit 12 or CMOS bit 57
127
HSMB_TX_D_N12
AU31
LVDS or 2.5-V LVDS TX bit 12n or CMOS bit 58
128
HSMB_RX_D_N12
AV27
LVDS or 2.5-V LVDS RX bit 12n or CMOS bit 59
131
HSMB_TX_D_P13
AR27
LVDS or 2.5-V LVDS TX bit 13 or CMOS bit 60
132
HSMB_RX_D_P13
AW32
LVDS or 2.5-V LVDS RX bit 13 or CMOS bit 61
133
HSMB_TX_D_N13
AP27
LVDS or 2.5-V LVDS TX bit 13n or CMOS bit 62
134
HSMB_RX_D_N13
AW33
LVDS or 2.5-V LVDS RX bit 13n or CMOS bit 63
137
HSMB_TX_D_P14
AP31
LVDS or 2.5-V LVDS TX bit 14 or CMOS bit 64
138
HSMB_RX_D_P14
AT31
LVDS or 2.5-V LVDS RX bit 14 or CMOS bit 65
139
HSMB_TX_D_N14
AN31
LVDS or 2.5-V LVDS TX bit 14n or CMOS bit 66
140
HSMB_RX_D_N14
AR31
LVDS or 2.5-V LVDS RX bit 14n or CMOS bit 67
143
HSMB_TX_D_P15
AP32
LVDS or 2.5-V LVDS TX bit 15 or CMOS bit 68
144
HSMB_RX_D_P15
AV28
LVDS or 2.5-V LVDS RX bit 15 or CMOS bit 69
145
HSMB_TX_D_N15
AN32
LVDS or 2.5-V LVDS TX bit 15n or CMOS bit 70
Table 2–46. HSMC Port B Pin Assignments, Schematic Signal Names, and Functions (Part 3 of 4)
Board
Reference (J2)
Schematic Signal Name
Arria V GX
FPGA
Pin Number
I/O Standard
Description