Featured device: arria v gx fpga, Featured device: arria v gx fpga –6 – Altera Arria V GX FPGA Development Board User Manual
Page 16
2–6
Chapter 2: Board Components
Featured Device: Arria V GX FPGA
Arria V GX FPGA Development Board
November 2013
Altera Corporation
Reference Manual
Featured Device: Arria V GX FPGA
The Arria V GX FPGA development board features two Arria V GX FPGA
5AGXFB3HF40 device (U13 and U16) in a 1517-pin FBGA package.
f
For more information about Arria V device family, refer to the
describes the features of the Arria V GX FPGA 5AGXFB3HF40 device.
lists the Arria V GX FPGA component reference and manufacturing
information.
Table 2–2. Arria V GX FPGA Features
ALMs
Equivalent
LEs
M10K RAM
Blocks
Total RAM
Kbits
18-bit × 18-bit
Multipliers
PLLs
Transceivers
Package Type
136,880
362,000
17,260
19,358
2,090
12
24
1517-pin FBGA
Table 2–3. Arria V GX FPGA Component Reference and Manufacturing Information
Board Reference
Description
Manufacturer
Manufacturing
Part Number
Manufacturer
Website
U13, U16
FPGA, Arria V GX F1517,
362K LEs, leadfree
Altera
Corporation
5AGXFB3HF40
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)