beautypg.com

Altera Arria V GX FPGA Development Board User Manual

Page 75

background image

Chapter 2: Board Components

2–65

Memory

November 2013

Altera Corporation

Arria V GX FPGA Development Board

Reference Manual

Table 2–56

lists the DDR3C (x64 soft controller) pin assignments, signal names, and

functions. The signal names and types are relative to the Arria V GX FPGA in terms of
I/O setting and direction.

D3

DDR3B_DM3

J29

1.5-V SSTL Class I

Write mask byte lane

E3

DDR3B_DQ16

P27

1.5-V SSTL Class I

Data bus byte lane

F7

DDR3B_DQ17

R27

1.5-V SSTL Class I

Data bus byte lane

F2

DDR3B_DQ18

H27

1.5-V SSTL Class I

Data bus byte lane

F8

DDR3B_DQ19

B27

1.5-V SSTL Class I

Data bus byte lane

H3

DDR3B_DQ20

C27

1.5-V SSTL Class I

Data bus byte lane

H8

DDR3B_DQ21

E27

1.5-V SSTL Class I

Data bus byte lane

G2

DDR3B_DQ22

M27

1.5-V SSTL Class I

Data bus byte lane

H7

DDR3B_DQ23

N27

1.5-V SSTL Class I

Data bus byte lane

D7

DDR3B_DQ24

C26

1.5-V SSTL Class I

Data bus byte lane

C3

DDR3B_DQ25

D26

1.5-V SSTL Class I

Data bus byte lane

C8

DDR3B_DQ26

K25

1.5-V SSTL Class I

Data bus byte lane

C2

DDR3B_DQ27

R26

1.5-V SSTL Class I

Data bus byte lane

A7

DDR3B_DQ28

T27

1.5-V SSTL Class I

Data bus byte lane

A2

DDR3B_DQ29

A26

1.5-V SSTL Class I

Data bus byte lane

B8

DDR3B_DQ30

F26

1.5-V SSTL Class I

Data bus byte lane

A3

DDR3B_DQ31

G26

1.5-V SSTL Class I

Data bus byte lane

G3

DDR3B_DQS_N2

T28

1.5-V SSTL Class I

Data strobe N byte lane

B7

DDR3B_DQS_N3

N26

1.5-V SSTL Class I

Data strobe N byte lane

F3

DDR3B_DQS_P2

R28

1.5-V SSTL Class I

Data strobe P byte lane

C7

DDR3B_DQS_P3

M26

1.5-V SSTL Class I

Data strobe P byte lane

Table 2–55. DDR3 x32 Devices Pin Assignments, Schematic Signal Names, and Functions (Part 3 of 3)

Board Reference

Schematic

Signal Name

Arria V GX FPGA

Pin Number

I/O Standard

Description

Table 2–56. DDR3 x64 Devices Pin Assignments, Schematic Signal Names, and Functions (Part 1 of 3)

Board Reference

Schematic

Signal Name

Arria V GX FPGA

Pin Number

I/O Standard

Description

DDR3C (U19, U22)

N3

DDR3B_A0

B31

1.5-V SSTL Class I

Address bus

P7

DDR3B_A1

A30

1.5-V SSTL Class I

Address bus

P3

DDR3B_A2

A31

1.5-V SSTL Class I

Address bus

N2

DDR3B_A3

A32

1.5-V SSTL Class I

Address bus

P8

DDR3B_A4

A33

1.5-V SSTL Class I

Address bus

P2

DDR3B_A5

B33

1.5-V SSTL Class I

Address bus

R8

DDR3B_A6

H31

1.5-V SSTL Class I

Address bus

R2

DDR3B_A7

J31

1.5-V SSTL Class I

Address bus

T8

DDR3B_A8

C31

1.5-V SSTL Class I

Address bus

R3

DDR3B_A9

D31

1.5-V SSTL Class I

Address bus