Altera Arria V GX FPGA Development Board - Manual (Page 37)

Chapter 2: Board Components 2–27
Clock Circuitry
November 2013 Altera Corporation Arria V GX FPGA Development Board
Reference Manual
Off-Board Clock Input/Output
The development board has input and output clocks which can be driven onto the
board. The output clocks can be programmed to different levels and I/O standards
according to the FPGA device’s specification.
Table 2–22 lists the clock inputs for the development board.
U34
REFCLK4_B_QL2_P
625.000 MHz
LVDS U31
C2C
REFCLK4_B_QL2_N LVDS U32
REFCLK2_B_QL1_P
100.000 MHz
LVDS AC31
C2C
REFCLK2_B_QL1_N LVDS AC32
REFCLK0_B_QL0_P
625.000 MHz
LVDS AG32
C2C
REFCLK0_B_QL0_N LVDS AG33
CLKINBOTB_P1
125.000 MHz
LVDS AL20
Bottom edge FPGA 2 – memory
CLKINBOTB_N1 LVDS AK20
U52
REFCLK3_B_QR2_P
125.000 MHz
LVDS T9
FMC
REFCLK3_B_QR2_N LVDS T8
REFCLK2_B_QR1_P
100.000 MHz
LVDS Y9
FMC
REFCLK2_B_QR1_N LVDS Y8
REFCLK1_B_QR0_P
156.250 MHz
LVDS AD9
HSMC port B, SDI
REFCLK1_B_QR0_N LVDS AD8
CLKINTOPB_P1
125.000 MHz
LVDS H6
Top edge FPGA 2
CLKINTOPB_N1 LVDS J6
Table 2–21. On-Board Oscillators
Source
Schematic Signal
Name
Frequency I/O Standard
Arria V GX
FPGA Pin
Number
Application
Table 2–22. Off-Board Clock Inputs
Source
Schematic Signal
Name
I/O Standard
Arria V GX
FPGA Pin
Number
Description
SMA
CLKIN_SMA_P LVPECL — Input to LVDS fan-out buffer (drives one REFCLK,
one clock on the top edge and one on the bottom
edge of each FPGA)
CLKIN_SMA_N LVPECL —
HSMC HSMA_CLK_IN0 2.5-V AT7
Single-ended input from the installed HSMC cable
or board.
HSMC
HSMA_CLK_IN_P1 LVDS/2.5-V AW4 LVDS input from the installed HSMC cable or
board. Can also support 2x LVTTL inputs.
HSMA_CLK_IN_N1 LVDS/LVTTL AV4
HSMC
HSMA_CLK_IN_P2 LVDS/LVTTL AR6 LVDS input from the installed HSMC cable or
board. Can also support 2x LVTTL inputs.
HSMA_CLK_IN_N2 LVDS/LVTTL AP6
HSMC HSMB_CLK_IN0 2.5-V AR6
Single-ended input from the installed HSMC cable
or board.
HSMC
HSMB_CLK_IN_P1 LVDS/LVTTL AM33 LVDS input from the installed HSMC cable or
board. Can also support 2x LVTTL inputs.
HSMB_CLK_IN_N1 LVDS/LVTTL AL33