Altera Arria V GX FPGA Development Board - Manual (Page 70)

2–60 Chapter 2: Board Components
Memory
Arria V GX FPGA Development Board November 2013 Altera Corporation
Reference Manual
M2 DDR3A_A7 K30 1.5-V SSTL Class I Address bus
N8 DDR3A_A8 D21 1.5-V SSTL Class I Address bus
M3 DDR3A_A9 M30 1.5-V SSTL Class I Address bus
H7 DDR3A_A10 J28 1.5-V SSTL Class I Address bus
M7 DDR3A_A11 M21 1.5-V SSTL Class I Address bus
K7 DDR3A_A12 G28 1.5-V SSTL Class I Address bus
N3 DDR3A_A13 M31 1.5-V SSTL Class I Address bus
J2 DDR3A_BA0 G30 1.5-V SSTL Class I Bank address bus
K8 DDR3A_BA1 T24 1.5-V SSTL Class I Bank address bus
J3 DDR3A_BA2 K34 1.5-V SSTL Class I Bank address bus
G3 DDR3A_CASN D32 1.5-V SSTL Class I Row address select
G9 DDR3A_CKE K29 1.5-V SSTL Class I Column address select
G7 DDR3A_CLK_N F34 1.5-V SSTL Class I Differential output clock
F7 DDR3A_CLK_P E34 1.5-V SSTL Class I Differential output clock
H2 DDR3A_CSN F31 1.5-V SSTL Class I Chip select
B7 DDR3A_DM8 P22 1.5-V SSTL Class I Write mask byte lane
B3 DDR3A_DQ64 B22 1.5-V SSTL Class I Data bus byte lane
C7 DDR3A_DQ65 L22 1.5-V SSTL Class I Data bus byte lane
C2 DDR3A_DQ66 C22 1.5-V SSTL Class I Data bus byte lane
C8 DDR3A_DQ67 N22 1.5-V SSTL Class I Data bus byte lane
E3 DDR3A_DQ68 E22 1.5-V SSTL Class I Data bus byte lane
E8 DDR3A_DQ69 J22 1.5-V SSTL Class I Data bus byte lane
D2 DDR3A_DQ70 A23 1.5-V SSTL Class I Data bus byte lane
E7 DDR3A_DQ71 F22 1.5-V SSTL Class I Data bus byte lane
D3 DDR3A_DQS_N8 D23 1.5-V SSTL Class I Data strobe N byte lane
C3 DDR3A_DQS_P8 C23 1.5-V SSTL Class I Data strobe P byte lane
G1 DDR3A_ODT E33 1.5-V SSTL Class I On-die termination enable
F3 DDR3A_RASN A32 1.5-V SSTL Class I Row address select
N2 DDR3A_RESETN J31 1.5-V SSTL Class I Reset
H3 DDR3A_WEN G29 1.5-V SSTL Class I Write enable
H8 DDR3A_ZQ05 — 1.5-V SSTL Class I ZQ impedance calibration
DDR3A (U11)
E7 DDR3A_DM6 M32 1.5-V SSTL Class I Write mask byte lane
D3 DDR3A_DM7 D31 1.5-V SSTL Class I Write mask byte lane
E3 DDR3A_DQ48 T26 1.5-V SSTL Class I Data bus byte lane
F7 DDR3A_DQ49 R24 1.5-V SSTL Class I Data bus byte lane
F2 DDR3A_DQ50 D25 1.5-V SSTL Class I Data bus byte lane
F8 DDR3A_DQ51 T25 1.5-V SSTL Class I Data bus byte lane
H3 DDR3A_DQ52 E25 1.5-V SSTL Class I Data bus byte lane
Table 2–54. DDR3A Devices Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 5)
Board Reference
Schematic
Signal Name
Arria V GX FPGA
Pin Number
I/O Standard Description