Altera Arria V GX FPGA Development Board - Manual (Page 13)

Chapter 2: Board Components 2–3
Board Overview
November 2013 Altera Corporation Arria V GX FPGA Development Board
Reference Manual
SW8
FPGA 1 mode select DIP
switch Sets the Arria V MSEL[4,2,1] pins. This switch is located on the
bottom of the board.
SW4
FPGA 2 mode select DIP
switch Sets the Arria V MSEL[4,2,1] pins. This switch is located on the
bottom of the board.
S2 Image select push button
Toggles the configuration LEDs which selects the program image that
loads from flash memory to the FPGA.
S3
Program configuration push
button Configures the FPGA from flash memory image based on the program
LEDs.
D1 Power LED Illuminates when 5.0-V power is present.
D2, D3 JTAG Tx/Rx LEDs
Indicate the transmit or receive activity of the JTAG chain. The Tx and
Rx LEDs blink when the link is in use and active. The LEDs are off when
not in use and on when in use or idle.
D4, D5 HSMC port A LEDs You can configure these LEDs to indicate transmit or receive activity.
D6 HSMC port A present LED Illuminates when a daughtercard is plugged into the HSMC port A.
D7, D8 HSMC port B LEDs You can configure these LEDs to indicate transmit or receive activity.
D9 HSMC port B present LED Illuminates when a daughtercard is plugged into the HSMC port B.
D10, D11 System Console Tx/Rx LEDs
Indicate the transmit or receive activity of the System Console USB
interface. The Tx and Rx LEDs blink when the link is in use and active.
The LEDs are off when not in use and on when in use or idle.
D12, D13, D14 Configuration LEDs
Illuminates to show the LED sequence that determines which flash
memory image loads to the FPGA when you press the PGM1_SEL push
button.
D15 Error LED Illuminates when the FPGA configuration from flash memory fails.
D16 Configuration done LED Illuminates when the FPGA is configured.
D17 Load LED
Illuminates when the MAX II CPLD EPM2210 System Controller is
actively configuring the FPGA.
D36, D37, D38,
D39, D40
Ethernet LEDs Shows the connection speed as well as transmit or receive activity.
D42, D43, D44 PCI Express link LEDs
You can configure these LEDs to display the PCI Express link width
(x1, x4, x8).
Clock Circuitry
U48
Si5338 programmable
oscillator
Programmable oscillator with default frequencies of CLK0=125 MHz,
CLK1=100 MHz, CLK2=625 MHz, CLK3=125 MHz at I
2 C address
71 HEX. The frequency is programmable using the clock GUI with the
default MAX II CPLD EPM2210 System Controller design programmed
into the MAX II EPM2210.
U53
Si5338 programmable
oscillator
Programmable oscillator with default frequencies of CLK0=625 MHz,
CLK1=156.25 MHz, CLK2=125 MHz, CLK3=125 MHz at I
2 C address
70 HEX. The frequency is programmable using the clock GUI with the
default MAX II CPLD EPM2210 System Controller design programmed
into the MAX II EPM2210.
U52
Si5338 programmable
oscillator
Programmable oscillator with default frequencies of CLK0=125 MHz,
CLK1=100 MHz, CLK2=156.25 MHz, CLK3=125 MHz at I
2 C address
73 HEX. The frequency is programmable using the clock GUI with the
default MAX II CPLD EPM2210 System Controller design programmed
into the MAX II EPM2210.
Table 2–1. Arria V GX FPGA Development Board Components (Part 2 of 4)
Board Reference Type Description