Altera Arria V GX FPGA Development Board - Manual (Page 54)

2–44 Chapter 2: Board Components
Components and Interfaces
Arria V GX FPGA Development Board November 2013 Altera Corporation
Reference Manual
33 HSMA_SDA AT14 2.5-V CMOS Management serial data
34 HSMA_SCL AU15 2.5-V CMOS Management serial clock
35 JTAG_TCK AV34 2.5-V CMOS JTAG clock signal
36 HSMA_JTAG_TMS — 2.5-V CMOS JTAG mode select signal
37 HSMA_JTAG_TDO — 2.5-V CMOS JTAG data output
38 AVB_JTAG_TDO AT34 2.5-V CMOS JTAG data output
39 HSMA_CLK_OUT0 AL14 LVDS or 2.5-V Dedicated CMOS clock out
40 HSMA_CLK_IN0 AT7 LVDS or 2.5-V Dedicated CMOS clock in
41 HSMA_D0 AG16 2.5-V CMOS Dedicated CMOS I/O bit 0
42 HSMA_D1 AH16 2.5-V CMOS Dedicated CMOS I/O bit 1
43 HSMA_D2 AV13 2.5-V CMOS Dedicated CMOS I/O bit 2
44 HSMA_D3 AW13 2.5-V CMOS Dedicated CMOS I/O bit 3
47 HSMA_TX_D_P0 AV6 LVDS or 2.5-V LVDS TX bit 0 or CMOS bit 4
48 HSMA_RX_D_P0 AW12 LVDS or 2.5-V LVDS RX bit 0 or CMOS bit 5
49 HSMA_TX_D_N0 AV7 LVDS or 2.5-V LVDS TX bit 0n or CMOS bit 6
50 HSMA_RX_D_N0 AV12 LVDS or 2.5-V LVDS RX bit 0n or CMOS bit 7
53 HSMA_TX_D_P1 AU6 LVDS or 2.5-V LVDS TX bit 1 or CMOS bit 8
54 HSMA_RX_D_P1 AR18 LVDS or 2.5-V LVDS RX bit 1 or CMOS bit 9
55 HSMA_TX_D_N1 AT6 LVDS or 2.5-V LVDS TX bit 1n or CMOS bit 10
56 HSMA_RX_D_N1 AP18 LVDS or 2.5-V LVDS RX bit 1n or CMOS bit 11
59 HSMA_TX_D_P2 AU9 LVDS or 2.5-V LVDS TX bit 2 or CMOS bit 12
60 HSMA_RX_D_P2 AU8 LVDS or 2.5-V LVDS RX bit 2 or CMOS bit 13
61 HSMA_TX_D_N2 AT9 LVDS or 2.5-V LVDS TX bit 2n or CMOS bit 14
62 HSMA_RX_D_N2 AU7 LVDS or 2.5-V LVDS RX bit 2n or CMOS bit 15
65 HSMA_TX_D_P3 AV10 LVDS or 2.5-V LVDS TX bit 3 or CMOS bit 16
66 HSMA_RX_D_P3 AW8 LVDS or 2.5-V LVDS RX bit 3 or CMOS bit 17
67 HSMA_TX_D_N3 AU10 LVDS or 2.5-V LVDS TX bit 3n or CMOS bit 18
68 HSMA_RX_D_N3 AW7 LVDS or 2.5-V LVDS RX bit 3n or CMOS bit 19
71 HSMA_TX_D_P4 AU12 LVDS or 2.5-V LVDS TX bit 4 or CMOS bit 20
72 HSMA_RX_D_P4 AW9 LVDS or 2.5-V LVDS RX bit 4 or CMOS bit 21
73 HSMA_TX_D_N4 AT12 LVDS or 2.5-V LVDS TX bit 4n or CMOS bit 22
74 HSMA_RX_D_N4 AV9 LVDS or 2.5-V LVDS RX bit 4n or CMOS bit 23
77 HSMA_TX_D_P5 AP9 LVDS or 2.5-V LVDS TX bit 5 or CMOS bit 24
78 HSMA_RX_D_P5 AU11 LVDS or 2.5-V LVDS RX bit 5 or CMOS bit 25
79 HSMA_TX_D_N5 AN9 LVDS or 2.5-V LVDS TX bit 5n or CMOS bit 26
80 HSMA_RX_D_N5 AT11 LVDS or 2.5-V LVDS RX bit 5n or CMOS bit 27
83 HSMA_TX_D_P6 AP12 LVDS or 2.5-V LVDS TX bit 6 or CMOS bit 28
84 HSMA_RX_D_P6 AR9 LVDS or 2.5-V LVDS RX bit 6 or CMOS bit 29
Table 2–45. HSMC Port A Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 4)
Board
Reference (J1)
Schematic Signal Name
Arria V GX
FPGA
Pin Number
I/O Standard Description