Altera Arria V GX FPGA Development Board - Manual (Page 55)

Chapter 2: Board Components 2–45
Components and Interfaces
November 2013 Altera Corporation Arria V GX FPGA Development Board
Reference Manual
85 HSMA_TX_D_N6 AN12 LVDS or 2.5-V LVDS TX bit 6n or CMOS bit 30
86 HSMA_RX_D_N6 AT8 LVDS or 2.5-V LVDS RX bit 6n or CMOS bit 31
89 HSMA_TX_D_P7 AM9 LVDS or 2.5-V LVDS TX bit 7 or CMOS bit 32
90 HSMA_RX_D_P7 AW5 LVDS or 2.5-V LVDS RX bit 7 or CMOS bit 33
91 HSMA_TX_D_N7 AL9 LVDS or 2.5-V LVDS TX bit 7n or CMOS bit 34
92 HSMA_RX_D_N7 AW6 LVDS or 2.5-V LVDS RX bit 7n or CMOS bit 35
95 HSMA_CLK_OUT_P1 AU13 LVDS or 2.5-V LVDS or CMOS clock out 1 or CMOS bit 36
96 HSMA_CLK_IN_P1 AW4 LVDS or 2.5-V LVDS or CMOS clock in 1 or CMOS bit 37
97 HSMA_CLK_OUT_N1 AT13 LVDS or 2.5-V LVDS or CMOS clock out 1 or CMOS bit 38
98 HSMA_CLK_IN_N1 AV4 LVDS or 2.5-V LVDS or CMOS clock in 1 or CMOS bit 39
101 HSMA_TX_D_P8 AL8 LVDS or 2.5-V LVDS TX bit 8 or CMOS bit 40
102 HSMA_RX_D_P8 AW11 LVDS or 2.5-V LVDS RX bit 8 or CMOS bit 41
103 HSMA_TX_D_N8 AK8 LVDS or 2.5-V LVDS TX bit 8n or CMOS bit 42
104 HSMA_RX_D_N8 AW10 LVDS or 2.5-V LVDS RX bit 8n or CMOS bit 43
107 HSMA_TX_D_P9 AK10 LVDS or 2.5-V LVDS TX bit 9 or CMOS bit 44
108 HSMA_RX_D_P9 AR10 LVDS or 2.5-V LVDS RX bit 9 or CMOS bit 45
109 HSMA_TX_D_N9 AK9 LVDS or 2.5-V LVDS TX bit 9n or CMOS bit 46
110 HSMA_RX_D_N9 AP10 LVDS or 2.5-V LVDS RX bit 9n or CMOS bit 47
113 HSMA_TX_D_P10 AL11 LVDS or 2.5-V LVDS TX bit 10 or CMOS bit 48
114 HSMA_RX_D_P10 AM10 LVDS or 2.5-V LVDS RX bit 10 or CMOS bit 49
115 HSMA_TX_D_N10 AK11 LVDS or 2.5-V LVDS TX bit 10n or CMOS bit 50
116 HSMA_RX_D_N10 AL10 LVDS or 2.5-V LVDS RX bit 10n or CMOS bit 51
119 HSMA_TX_D_P11 AL12 LVDS or 2.5-V LVDS TX bit 11 or CMOS bit 52
120 HSMA_RX_D_P11 AJ13 LVDS or 2.5-V LVDS RX bit 11 or CMOS bit 53
121 HSMA_TX_D_N11 AK12 LVDS or 2.5-V LVDS TX bit 11n or CMOS bit 54
122 HSMA_RX_D_N11 AH13 LVDS or 2.5-V LVDS RX bit 11n or CMOS bit 55
125 HSMA_TX_D_P12 AM13 LVDS or 2.5-V LVDS TX bit 12 or CMOS bit 56
126 HSMA_RX_D_P12 AH11 LVDS or 2.5-V LVDS RX bit 12 or CMOS bit 57
127 HSMA_TX_D_N12 AL13 LVDS or 2.5-V LVDS TX bit 12n or CMOS bit 58
128 HSMA_RX_D_N12 AG11 LVDS or 2.5-V LVDS RX bit 12n or CMOS bit 59
131 HSMA_TX_D_P13 AE12 LVDS or 2.5-V LVDS TX bit 13 or CMOS bit 60
132 HSMA_RX_D_P13 AG12 LVDS or 2.5-V LVDS RX bit 13 or CMOS bit 61
133 HSMA_TX_D_N13 AD12 LVDS or 2.5-V LVDS TX bit 13n or CMOS bit 62
134 HSMA_RX_D_N13 AF12 LVDS or 2.5-V LVDS RX bit 13n or CMOS bit 63
137 HSMA_TX_D_P14 AD11 LVDS or 2.5-V LVDS TX bit 14 or CMOS bit 64
138 HSMA_RX_D_P14 AD13 LVDS or 2.5-V LVDS RX bit 14 or CMOS bit 65
139 HSMA_TX_D_N14 AC12 LVDS or 2.5-V LVDS TX bit 14n or CMOS bit 66
140 HSMA_RX_D_N14 AC13 LVDS or 2.5-V LVDS RX bit 14n or CMOS bit 67
Table 2–45. HSMC Port A Pin Assignments, Schematic Signal Names, and Functions (Part 3 of 4)
Board
Reference (J1)
Schematic Signal Name
Arria V GX
FPGA
Pin Number
I/O Standard Description