Altera Arria V GX FPGA Development Board User Manual
Page 48

2–38
Chapter 2: Board Components
Components and Interfaces
Arria V GX FPGA Development Board
November 2013
Altera Corporation
Reference Manual
shows the PCI Express reference clock levels.
The JTAG and SMB are optional signals in the PCI Express specification. Therefore,
the JTAG signal loopback from PCI Express TDI to PCI Express TDO and are not used
on this board. The SMB signals are wired to the Arria V GX FPGA but are not required
for normal operation.
summarizes the PCI Express pin assignments. The signal names and
directions are relative to the Arria V GX FPGA.
Figure 2–8. PCI Express Reference Clock Levels
V
MAX
= 1.15 V
V
CROSS MAX
= 550 mV
V
CROSS MIN
= 250 mV
V
MIN
= –0.30 V
REFCLK –
REFCLK +
Table 2–41. PCI Express Pin Assignments, Schematic Signal Names, and Functions
Board
Reference (J4)
Schematic Signal Name
Arria V GX FPGA
Pin Number
I/O Standard
Description
A5
PCIE_JTAG_TCK
—
1.5-V PCML
JTAG chain clock
A6
PCIE_JTAG_TDI
—
1.5-V PCML
JTAG chain data in
A7
PCIE_JTAG_TDO
—
1.5-V PCML
JTAG chain data out
A8
PCIE_JTAG_TMS
—
1.5-V PCML
JTAG chain mode select
A11
PCIE_PERSTN
N9
1.5-V PCML
Presence detect DIP switch
A1
PCIE_PRSNT1N
—
1.5-V PCML
Presence detect DIP switch
B17
PCIE_PRSNT2N_X1
—
1.5-V PCML
Presence detect DIP switch
B31
PCIE_PRSNT2N_X4
—
1.5-V PCML
Presence detect DIP switch
B48
PCIE_PRSNT2N_X8
—
1.5-V PCML
Presence detect DIP switch
A14
PCIE_REFCLK_N
AG33
1.5-V PCML
Motherboard reference clock
A13
PCIE_REFCLK_P
AG32
1.5-V PCML
Motherboard reference clock
B15
PCIE_RX_N0
AW36
1.5-V PCML
Receive bus
B20
PCIE_RX_N1
AT38
1.5-V PCML
Receive bus
B24
PCIE_RX_N2
AP38
1.5-V PCML
Receive bus
B28
PCIE_RX_N3
AM38
1.5-V PCML
Receive bus
B34
PCIE_RX_N4
AH38
1.5-V PCML
Receive bus
B38
PCIE_RX_N5
AF38
1.5-V PCML
Receive bus
B42
PCIE_RX_N6
AD38
1.5-V PCML
Receive bus
B46
PCIE_RX_N7
AB38
1.5-V PCML
Receive bus
B14
PCIE_RX_P0
AW37
1.5-V PCML
Receive bus
B19
PCIE_RX_P1
AT39
1.5-V PCML
Receive bus
B23
PCIE_RX_P2
AP39
1.5-V PCML
Receive bus