Altera Arria V GX FPGA Development Board - Manual (Page 47)

Chapter 2: Board Components 2–37
Components and Interfaces
November 2013 Altera Corporation Arria V GX FPGA Development Board
Reference Manual
Components and Interfaces
This section describes the development board's communication ports and interface
cards relative to the Arria V GX FPGA. The development board supports the
following communication ports:
■ PCI Express
■ 10/100/1000 Ethernet
■ HSMC
■ SFP+ module
■ FMC connector
■ Bull’s Eye connector
PCI Express
The Arria V GX FPGA development board is designed to fit entirely into a PC
motherboard with a ×8 PCI Express slot that can accommodate a full height long form
factor add-in card. This interface uses the Arria V GX FPGA's PCI Express hard IP
block, saving logic resources for the user logic application. The PCI express edge
connector has a presence detect feature to allow the motherboard to determine if a
card is installed.
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For more information on using the PCI Express hard IP block, refer to the PCI Express
Compiler User Guide .
The PCI Express interface supports auto-negotiating channel width from ×1 to ×4 to
×8 by using Altera's PCIe MegaCore IP. You can also configure this board to a ×1, ×4,
or ×8 interface through a DIP switch that connects the PRSNTn pins for each bus width.
The PCI Express edge connector has a connection speed of 2.5 Gbps/lane for a
maximum of 20 Gbps full-duplex (Gen1) or 5.0 Gbps/lane for a maximum of 40 Gbps
full-duplex (Gen2).
The power for the board can be sourced entirely from the PCI Express edge connector
when installed into a PC motherboard. Although the board can also be powered by a
laptop power supply for use on a lab bench, Altera recommends that you do not
power up from both supplies at the same time. Ideal diode power sharing devices
have been designed into this board to prevent damages or back-current from one
supply to the other.
The PCIE_REFCLK_P signal is a 100 MHz differential input that is driven from the PC
motherboard on to this board through the edge connector. This signal connects
directly to a Arria V GX FPGA REFCLK input pin pair using DC coupling. This clock is
terminated on the motherboard and therefore, no on-board termination is required.
This clock can have spread-spectrum properties that change its period between
9.847 ps to 10.203 ps. The I/O standard is High-Speed Current Steering Logic (HCSL).