Altera Cyclone V E FPGA Development Board - Manual (Page 6)

1–2 Chapter 1: Overview
Board Component Blocks
Cyclone V E FPGA Development Board March 2013 Altera Corporation
Reference Manual
Board Component Blocks
The development board features the following major component blocks:
■ One Cyclone V E FPGA (5CEFA7F31I7N) in a 896-pin FineLine BGA (FBGA)
package
■ 149,500 LEs
■ 56,480 adaptive logic modules (ALMs)
■ 6,860 Kbit (Kb) M10K and 836 Kb MLAB memory
■ Seven fractional phase locked loops (PLLs)
■ 312 18x18-bit multipliers
■ 480 general purpose input/output (GPIO)
■ 1.1-V core voltage
■ FPGA configuration circuitry
■ Active Serial (AS) x1 or AS x4 configuration (EPCQ256SI16N)
■ MAX ® V CPLD (5M2210ZF256I5N) in a 256-pin FBGA package as the System
Controller
■ Flash fast passive parallel (FPP) configuration
■ MAX II CPLD (EPM240M100I5N) in a 100-pin FBGA package as part of the
embedded USB-Blaster
TM II for use with the Quartus ® II Programmer
■ Clocking circuitry
■ Programmable clock generator for the FPGA reference clock input
■ 50-MHz single-ended oscillator for the FPGA and MAX V CPLD clock input
■ 100-MHz single-ended oscillator for the MAX V CPLD configuration clock
input
■ SMA input (LVDS)
■ Memory
■ Two 256-Mbyte (MB) DDR3 SDRAM devices with a 16-bit data bus
■ One 18-Mbit (Mb) SSRAM
■ One 512-Mb synchronous flash
■ One 512-MB LPDDR2 SDRAM with a 32-bit data bus (only 16-bit data bus is
used on this board)
■ One 64-Kb I 2 C serial electrically erasable PROM (EEPROM)