Altera Cyclone V E FPGA Development Board - Manual (Page 44)

2–36 Chapter 2: Board Components
Memory
Cyclone V E FPGA Development Board March 2013 Altera Corporation
Reference Manual
T2 LPDDR2_CA8 T28 1.2-V HSUL Address bus
T1 LPDDR2_CA9 T25 1.2-V HSUL Address bus
Y2 LPDDR2_CK V21 Differential 1.2-V HSUL Differential output clock P
Y1 LPDDR2_CKN V22 Differential 1.2-V HSUL Differential output clock N
AC3 LPDDR2_CKE T29 1.2-V HSUL Clock enable
AB3 LPDDR2_CSN R26 1.2-V HSUL Chip select
N23 LPDDR2_DM0 AG29 1.2-V HSUL Data mask
L23 LPDDR2_DM1 AB27 1.2-V HSUL Data mask
AB20 LPDDR2_DM2 — 1.2-V HSUL Data mask
B20 LPDDR2_DM3 — 1.2-V HSUL Data mask
AA23 LPDDR2_DQ0 AG28 1.2-V HSUL Data bus byte lane 0
Y22 LPDDR2_DQ1 AH30 1.2-V HSUL Data bus byte lane 0
W22 LPDDR2_DQ2 AA28 1.2-V HSUL Data bus byte lane 0
W23 LPDDR2_DQ3 AH29 1.2-V HSUL Data bus byte lane 0
V23 LPDDR2_DQ4 Y28 1.2-V HSUL Data bus byte lane 0
U22 LPDDR2_DQ5 AE30 1.2-V HSUL Data bus byte lane 0
T22 LPDDR2_DQ6 AJ28 1.2-V HSUL Data bus byte lane 0
T23 LPDDR2_DQ7 AD30 1.2-V HSUL Data bus byte lane 0
H22 LPDDR2_DQ8 AC29 1.2-V HSUL Data bus byte lane 1
H23 LPDDR2_DQ9 AF30 1.2-V HSUL Data bus byte lane 1
G23 LPDDR2_DQ10 AA30 1.2-V HSUL Data bus byte lane 1
F22 LPDDR2_DQ11 AE28 1.2-V HSUL Data bus byte lane 1
E22 LPDDR2_DQ12 AF29 1.2-V HSUL Data bus byte lane 1
E23 LPDDR2_DQ13 AD28 1.2-V HSUL Data bus byte lane 1
D23 LPDDR2_DQ14 V27 1.2-V HSUL Data bus byte lane 1
C22 LPDDR2_DQ15 W28 1.2-V HSUL Data bus byte lane 1
AB12 LPDDR2_DQ16 — 1.2-V HSUL Data bus byte lane 2
AC13 LPDDR2_DQ17 — 1.2-V HSUL Data bus byte lane 2
AB14 LPDDR2_DQ18 — 1.2-V HSUL Data bus byte lane 2
AC14 LPDDR2_DQ19 — 1.2-V HSUL Data bus byte lane 2
AB15 LPDDR2_DQ20 — 1.2-V HSUL Data bus byte lane 2
AC16 LPDDR2_DQ21 — 1.2-V HSUL Data bus byte lane 2
AB17 LPDDR2_DQ22 — 1.2-V HSUL Data bus byte lane 2
AC17 LPDDR2_DQ23 — 1.2-V HSUL Data bus byte lane 2
B17 LPDDR2_DQ24 — 1.2-V HSUL Data bus byte lane 3
A17 LPDDR2_DQ25 — 1.2-V HSUL Data bus byte lane 3
A16 LPDDR2_DQ26 — 1.2-V HSUL Data bus byte lane 3
B15 LPDDR2_DQ27 — 1.2-V HSUL Data bus byte lane 3
B14 LPDDR2_DQ28 — 1.2-V HSUL Data bus byte lane 3
Table 2–25. LPDDR2 SDRAM Schematic Signal Names and Functions
Board
Reference (U9)
Schematic
Signal Name
Cyclone V E
FPGA Pin Number
I/O Standard Description