Altera Cyclone V E FPGA Development Board - Manual (Page 41)

Chapter 2: Board Components 2–33
Memory
March 2013 Altera Corporation Cyclone V E FPGA Development Board
Reference Manual
R7 DDR3_A11 E20 1.5-V SSTL Class I Address bus
N7 DDR3_A12 C25 1.5-V SSTL Class I Address bus
T3 DDR3_A13 B13 1.5-V SSTL Class I Address bus
M2 DDR3_BA0 J18 1.5-V SSTL Class I Bank address bus
N8 DDR3_BA1 F20 1.5-V SSTL Class I Bank address bus
M3 DDR3_BA2 D19 1.5-V SSTL Class I Bank address bus
K3 DDR3_CASN L20 1.5-V SSTL Class I Row address select
K9 DDR3_CKE C11 1.5-V SSTL Class I Column address select
J7 DDR3_CLK_P J20
Differential 1.5-V
SSTL Class I
Differential output clock
K7 DDR3_CLK_N H20
Differential 1.5-V
SSTL Class I
Differential output clock
L2 DDR3_CSN G17 1.5-V SSTL Class I Chip select
E7 DDR3_DM0 D23 1.5-V SSTL Class I Write mask byte lane
D3 DDR3_DM1 D18 1.5-V SSTL Class I Write mask byte lane
E3 DDR3_DQ0 A25 1.5-V SSTL Class I Data bus byte lane 0
H8 DDR3_DQ1 D22 1.5-V SSTL Class I Data bus byte lane 0
F7 DDR3_DQ2 C21 1.5-V SSTL Class I Data bus byte lane 0
H7 DDR3_DQ3 C19 1.5-V SSTL Class I Data bus byte lane 0
F2 DDR3_DQ4 C20 1.5-V SSTL Class I Data bus byte lane 0
G2 DDR3_DQ5 C22 1.5-V SSTL Class I Data bus byte lane 0
F8 DDR3_DQ6 D25 1.5-V SSTL Class I Data bus byte lane 0
H3 DDR3_DQ7 D20 1.5-V SSTL Class I Data bus byte lane 0
A7 DDR3_DQ8 B24 1.5-V SSTL Class I Data bus byte lane 1
C3 DDR3_DQ9 A21 1.5-V SSTL Class I Data bus byte lane 1
A3 DDR3_DQ10 B21 1.5-V SSTL Class I Data bus byte lane 1
D7 DDR3_DQ11 F19 1.5-V SSTL Class I Data bus byte lane 1
A2 DDR3_DQ12 C24 1.5-V SSTL Class I Data bus byte lane 1
C2 DDR3_DQ13 B23 1.5-V SSTL Class I Data bus byte lane 1
B8 DDR3_DQ14 E18 1.5-V SSTL Class I Data bus byte lane 1
C8 DDR3_DQ15 A23 1.5-V SSTL Class I Data bus byte lane 1
F3 DDR3_DQS_P0 K20
Differential 1.5-V
SSTL Class I
Data strobe P byte lane 0
G3 DDR3_DQS_N0 J19
Differential 1.5-V
SSTL Class I
Data strobe N byte lane 0
C7 DDR3_DQS_P1 L18
Differential 1.5-V
SSTL Class I
Data strobe P byte lane 1
B7 DDR3_DQS_N1 K18
Differential 1.5-V
SSTL Class I
Data strobe N byte lane 1
K1 DDR3_ODT H19 1.5-V SSTL Class I On-die termination enable
Table 2–24. DDR3 Device Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 4)
Board
Reference
Schematic
Signal Name
Cyclone V E FPGA
Pin Number
I/O Standard Description