Altera Cyclone V E FPGA Development Board - Manual (Page 42)

2–34 Chapter 2: Board Components
Memory
Cyclone V E FPGA Development Board March 2013 Altera Corporation
Reference Manual
J3 DDR3_RASN A24 1.5-V SSTL Class I Row address select
T2 DDR3_RESETN L19 1.5-V SSTL Class I Reset
L3 DDR3_WEN B22 1.5-V SSTL Class I Write enable
L8 DDR3_ZQ01 — 1.5-V SSTL Class I ZQ impedance calibration
DDR3 x16 (U7)
N3 DDR3_A0 A16 1.5-V SSTL Class I Address bus
P7 DDR3_A1 G23 1.5-V SSTL Class I Address bus
P3 DDR3_A2 E21 1.5-V SSTL Class I Address bus
N2 DDR3_A3 E22 1.5-V SSTL Class I Address bus
P8 DDR3_A4 A20 1.5-V SSTL Class I Address bus
P2 DDR3_A5 A26 1.5-V SSTL Class I Address bus
R8 DDR3_A6 A15 1.5-V SSTL Class I Address bus
R2 DDR3_A7 B26 1.5-V SSTL Class I Address bus
T8 DDR3_A8 H17 1.5-V SSTL Class I Address bus
R3 DDR3_A9 D14 1.5-V SSTL Class I Address bus
L7 DDR3_A10 E23 1.5-V SSTL Class I Address bus
R7 DDR3_A11 E20 1.5-V SSTL Class I Address bus
N7 DDR3_A12 C25 1.5-V SSTL Class I Address bus
T3 DDR3_A13 B13 1.5-V SSTL Class I Address bus
M2 DDR3_BA0 J18 1.5-V SSTL Class I Bank address bus
N8 DDR3_BA1 F20 1.5-V SSTL Class I Bank address bus
M3 DDR3_BA2 D19 1.5-V SSTL Class I Bank address bus
K3 DDR3_CASN L20 1.5-V SSTL Class I Row address select
K9 DDR3_CKE AK18 1.5-V SSTL Class I Column address select
K7 DDR3_CLK_P J20 1.5-V SSTL Class I Differential output clock
J7 DDR3_CLK_N H20 1.5-V SSTL Class I Differential output clock
L2 DDR3_CSN G17 1.5-V SSTL Class I Chip select
E7 DDR3_DM2 A19 1.5-V SSTL Class I Write mask byte lane
D3 DDR3_DM3 B14 1.5-V SSTL Class I Write mask byte lane
F2 DDR3_DQ16 G18 1.5-V SSTL Class I Data bus byte lane 2
F8 DDR3_DQ17 B18 1.5-V SSTL Class I Data bus byte lane 2
E3 DDR3_DQ18 A18 1.5-V SSTL Class I Data bus byte lane 2
F7 DDR3_DQ19 F18 1.5-V SSTL Class I Data bus byte lane 2
H3 DDR3_DQ20 C14 1.5-V SSTL Class I Data bus byte lane 2
G2 DDR3_DQ21 C17 1.5-V SSTL Class I Data bus byte lane 2
H7 DDR3_DQ22 B17 1.5-V SSTL Class I Data bus byte lane 2
H8 DDR3_DQ23 B19 1.5-V SSTL Class I Data bus byte lane 2
A2 DDR3_DQ24 C15 1.5-V SSTL Class I Data bus byte lane 3
Table 2–24. DDR3 Device Pin Assignments, Schematic Signal Names, and Functions (Part 3 of 4)
Board
Reference
Schematic
Signal Name
Cyclone V E FPGA
Pin Number
I/O Standard Description