Altera Cyclone V E FPGA Development Board - Manual (Page 35)

Chapter 2: Board Components 2–27
Components and Interfaces
March 2013 Altera Corporation Cyclone V E FPGA Development Board
Reference Manual
HSMC
The development board supports a HSMC interface. The HSMC interface supports a
full SPI4.2 interface (17 LVDS channels), three input and output clocks, as well as
JTAG and SMB signals. The LVDS channels can be used for CMOS signaling or LVDS.
1
The HSMC is an Altera-developed open specification, which allows you to expand
the functionality of the development board through the addition of daughtercards
(HSMCs).
f
For more information about the HSMC specification such as signaling standards,
signal integrity, compatible connectors, and mechanical information, refer to the
High
Speed Mezzanine Card (HSMC) Specification manual.
The HSMC connector has a total of 172 pins, including 120 signal pins, 39 power pins,
and 13 ground pins. The ground pins are located between the two rows of signal and
power pins, acting both as a shield and a reference. The HSMC host connector is
based on the 0.5 mm-pitch QSH/QTH family of high-speed, board-to-board
connectors from Samtec. There are three banks in this connector. Bank 1 has every
third pin removed as done in the QSH-DP/QTH-DP series. Bank 2 and bank 3 have
all the pins populated as done in the QSH/QTH series. Since the Cyclone V E FPGA
development board is not a transceiver board, the transceiver pins of the HSMC is not
connected to the Cyclone V E FPGA device.
Figure 2–8 shows the bank arrangement of signals with respect to the Samtec
connector's three banks.
42 ENETB_MDI_P3 — 2.5-V CMOS Media dependent interface
43 ENETB_MDI_N3 — 2.5-V CMOS Media dependent interface
Table 2–20. Ethernet PHY Pin Assignments, Signal Names and Functions (Part 3 of 3)
Board
Reference
Schematic Signal Name
Cyclone V E FPGA
Pin Number
I/O Standard Description
Figure 2–8. HSMC Signal and Bank Diagram
Bank 3
Power
D(79.40)
-or-
LVDS
CLKIN2, CLKOUT2
Bank 2
Power
D(39:0)
-or-
D[3:0] + LVDS
CLKIN1, CLKOUT1
Bank 1
8 TX Channels CDR
8 RX Channels CDR
JTAG
SMB
CLKIN0, CLKOUT0