Altera Interlaken MegaCore Function User Manual
Page 71

Appendix A: Initializing the Interlaken MegaCore Function
A–3
Troubleshooting an Interlaken Link
June 2012
Altera Corporation
Interlaken MegaCore Function
User Guide
■
If the lanes are locked and not generating CRC-32 errors, you can exchange traffic.
If IDLE symbols pass, but regular traffic generates numerous CRC-24 errors, the
lanes might be out of order. IDLE symbols are single word messages and therefore
not subject to ordering issues. However, multi-word messages generate CRC-24
errors when the lanes are out of order. Due to manufacturing constraints, boards
and adapters are often designed with scrambled lane order. Check that your
physical connections take these lane order differences into account.
See also other documents in the category Altera Measuring instruments:
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- Cyclone III FPGA Starter Kit (36 pages)
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- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
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- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
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- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
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- DCFIFO (28 pages)