Altera Interlaken MegaCore Function - Manual (Page 37)

Chapter 4: Functional Description 4–11
Transmit Path
June 2012 Altera Corporation Interlaken MegaCore Function
User Guide
For more information about the transceiver reference clock frequency, refer to the
ALTGX Transceiver Setup Guide chapter in volume 3 of the Stratix IV Device Handbook.
For information about high-speed transceiver blocks, refer to volume 2 and volume 3 of
the Stratix IV Device Handbook.
Out-of-Band Flow Control Block Recommended Clock Frequencies
The recommended frequency for the rx_oob_in_fc_clk and the tx_oob_out_clk
clocks is 100 MHz, which is the maximum frequency allowed by the Interlaken
specification.
The rx_oob_in_sys_clk frequency must be at least twice the rx_oob_in_fc_clk
frequency, and the tx_oob_in_double_fc_clk frequency must be twice the
tx_oob_out_clk
frequency. In consequence, the recommended frequency for the
rx_oob_in_sys_clk and tx_oob_in_double_fc_clk is 200 MHz.
Reset for Interlaken MegaCore Functions
The Interlaken MegaCore function has a single asynchronous reset, the reset_export
signal. You must assert the reset_export signal for at least four full cal_blk_clk
clock cycles to ensure complete reset of your Interlaken MegaCore function.
Following completion of the reset sequence internally, the Interlaken MegaCore
function begins link initialization. If your Interlaken MegaCore function and its
Interlaken link partner initialize the link successfully, you can observe the assertion of
the lane and link status signals according to the Interlaken specification.
For information about the internal reset sequence that you intiate when you assert the
reset_export
signal, refer to “Required Reset Sequence” on page B–8 . This section
describes the required reset sequence to reset the full Interlaken MegaCore function,
except the high-speed transceivers. However, the internal reset signals the sequence
drives do not appear as top-level signals in an Interlaken MegaCore function
variation that includes the high-speed transceivers. When you assert the
reset_export
signal, this sequence is driven internally and the high-speed
transceivers are reset.
1 Altera recommends that you turn off Global reset in a Qsys system that includes an
Interlaken MegaCore function. Instead, export the reset_export signal and assert it
from outside the Qsys system.
For more information about the link initialization sequence, refer to Table 5–2 on
page 5–3 and to Appendix A, Initializing the Interlaken MegaCore Function .
For more information about the global reset signal, refer to “Interlaken MegaCore
Function Reset Signals” on page 5–4 .
Transmit Path
The Interlaken MegaCore function receives application data on two application
channels. It combines the data from the two channels into a single data stream in
which data is labeled with its source channel. The Interlaken TX MAC and PCS blocks
format the data in protocol-compliant bursts and insert Idle words where required.