Altera Interlaken MegaCore Function - Manual (Page 69)

June 2012 Altera Corporation Interlaken MegaCore Function
User Guide
A. Initializing the Interlaken MegaCore
Function
This appendix describes a basic reset sequence for the Interlaken MegaCore function,
describes the expected sequence of signal assertions during initialization, and
provides some troubleshooting tips for the Interlaken link.
Configuration and Reset
This section describes the most basic initialization sequence for an Interlaken system
that contains two Interlaken MegaCore functions connected through their Interlaken
interfaces.
To initialize the system, perform the following steps:
1. Configure the devices with the two Interlaken MegaCore functions.
2. For each Interlaken MegaCore function, assert the reset_export signal to initiate
the internal reset sequence.
After the internal reset sequence completes, you should observe the behavior
described in
“Expected Behavior at Initialization” .
Expected Behavior at Initialization
After the internal reset sequence completes, as your Interlaken MegaCore function
initializes and establishes an Interlaken link with its link partner, you should observe
the following changes on the output signals:
1. For each lane i, status signals change in the following order:
a. rx_status_per_lane_word_lock[i] is asserted. This signal indicates the lane
has locked onto the three-bit synchronization header, which occurs when 64
consecutive legal sync patterns have been observed. This state is 64B/67B
Word Lock, shown in Figure 13 in the Interlaken Protocol Definition, Revision 1.2.
b. rx_status_per_lane_sync_lock[i] is asserted. This signal indicates the lane
has locked onto the meta frame boundary and recovered the scrambler seed
from incoming traffic. This state is RX LaneValid, shown in Figure 8 in the
Interlaken Protocol Definition, Revision 1.2.
2. After rx_status_per_lane_word_lock[i] is asserted for every lane i (every lane
has achieved the 64B/67B Word Lock state), the rx_status_all_word_locked
signal is asserted.
3. After rx_status_per_lane_sync_lock[i] is asserted for every lane i (every lane
has achieved the RX LaneValid state), the rx_status_all_sync_locked signal is
asserted.