Altera Interlaken MegaCore Function - Manual (Page 7)

June 2012 Altera Corporation Interlaken MegaCore Function
User Guide
1. About This MegaCore Function
Interlaken is a high-speed serial communication protocol for chip-to-chip packet
transfers. The Altera
® Interlaken MegaCore ® function implements the Interlaken
Protocol Specification, Revision 1.2 . It supports specific combinations of number of lanes
from 4 to 20, and lane rates from 3.125 to 10.3125 gigabits per second (Gbps), on
Stratix
® IV GT devices, and lane rates from 3.125 to 6.375 Gbps on Stratix IV GX
devices, providing raw bandwidth of 12.50 Gbps to 127.50 Gbps.
Interlaken provides low I/O count compared to earlier protocols, supporting
scalability in both number of lanes and lane speed. Other key features include flow
control, low overhead framing, and extensive integrity checking. The Interlaken
MegaCore function incorporates a physical coding sublayer (PCS), a physical media
attachment (PMA), and a media access control (MAC) block. The MegaCore function
transmits and receives Avalon
® Streaming (Avalon-ST) data on its FPGA fabric
interface.
Figure 1–1 shows an example system implementation.
Features
The Interlaken MegaCore function has the following features:
■ Compliant with the Interlaken Protocol Specification, Rev 1.2
■ Supports 4, 8, 10, 12, and 20 serial lanes in configurations that provide nominal
bandwidths of 20 Gbps, 40 Gbps, and 100 Gbps
■ Supports per-lane data rates of 3.125, 6.25, 6.375, and 10.3125 Gbps using Altera
on-chip high-speed transceivers
Figure 1–1. Typical Interlaken Application
Interlaken
MegaCore
Function
Interlaken
MegaCore
Function
Stratix IV GT
FPGA
Stratix IV GX
FPGA
Memory
Controller
High-Speed
Memory
Ethernet MAC
Interlaken Link
Optical
Module
Swuitch F
abr
ic or Bac
kplane