Altera Interlaken MegaCore Function - Manual (Page 39)

Chapter 4: Functional Description 4–13
Transmit Path
June 2012 Altera Corporation Interlaken MegaCore Function
User Guide
In addition to incoming data, the arbiter receives start-of-packet and end-of-packet
indicators whose values apply to the data on tx_chX_datain_data in the current
tx_mac_c_clk
clock cycle, and an error indicator whose value is valid on the
end-of-packet clock cycle and which refers to the current packet.
The empty vector tx_chX_datain_empty indicates the number of invalid bytes in the
incoming data on tx_chX_datain_data in the current tx_mac_c_clk clock cycle. The
valid data must be in the most significant bytes of the data bus. Use of the
tx_chX_datain_empty
signal on non end-of-packet cycles is a modification of the
Avalon-ST interface protocol. This modification allows the application to provide the
Interlaken MegaCore function with incomplete words of valid data, mirroring the
same capability on the Interlaken link.
A two-bit signal, tx_control_channel_enable, allows the application to specify
independently for each channel whether the arbiter should accept or ignore its data.
The application can assert the tx_control_force_transmit signal to tell the arbiter to
ignore the RX calendar value when accepting or ignoring input data from the
application. These two signals provide input to an enable indicator for the channel.
The arbiter sends its interleaved stream of data to the TX MAC block. The information
sent out every tx_mac_c_clk clock cycle includes the data, start-of-packet and
end-of-packet indicators, and an indicator of the source channel for this data.
For more information about the arbiter signals, refer to “TX Application Interface
Signals” on page 5–6 .
Application Data Transfer Example
Figure 4–7 to Figure 4–10 show an example of a 1016-byte packet transfer on channel
0. For purposes of the example, assume that channel 1 is not in use
(tx_ch1_datain_valid is not asserted) or is disabled
(tx_control_channel_enable[1:0] has value 1). The tx_coreclkout clock signal
drives the tx_mac_c_clk clock, which is shown in the waveforms.
Figure 4–7 shows
the beginning of the packet transfer on channel 0, illustrating the interaction between
the tx_ch0_datain_valid and tx_ch0_datain_ready signal behavior at the beginning
of a packet transfer.
Figure 4–8 shows a point partway through the packet transfer, in
which the application is utilizing the Interlaken link fully. The Interlaken MegaCore
function backpressures the channel to prevent overflow.
Figure 4–9 shows a different
point partway through the packet transfer, at which the application deasserts the
valid signal when it does not have data ready for the arbiter. This delay causes the