Altera Interlaken MegaCore Function - Manual (Page 65)

Chapter 6: Qsys Design Examples 6–3
Design Example Simulation Sequence
June 2012 Altera Corporation Interlaken MegaCore Function
User Guide
The Interlaken Sample Channel Client maintains a string (TX_STRING) from which it
generates the data samples. It compares the returning data samples against another
string of the same length (RX_STRING). In the design examples, the data passes through
an Interlaken link external loopback path, and so the two strings are identical.
However, the Interlaken Sample Channel Client component is useful in additional
testing configurations. For example, you could create two instances of this
component, connected to two Interlaken MegaCore function Interlaken link partners,
to generate and check data samples at opposite ends of the link. In that case, you
would define the TX_STRING in each to be identical to the RX_STRING in the other.
Design Example Simulation Sequence
The design example performs the following transactions:
■ Activates the Interlaken Sample Channel Client on each of the two channels to
send data samples to the RX application interface of the Interlaken MegaCore
function. The channel client actions are described in
“Interlaken Sample Channel
Client Component” .
■ Confirms valid data is received by the sample channel client from the relevant
channel of the RX application interface of the Interlaken MegaCore function.
■ Keeps track of the count-stamp of the latest incoming data sample received, and
checks that the current data sample count-stamp is equal to the previous stamp
incremented by one.
■ Monitors the output from each channel of the RX application interface of the
Interlaken MegaCore function for CRC-24 and CRC-32 errors.
After the design example sends and receives 100 packets on each channel, with no
CRC-24 or CRC-32 errors, it declares success and terminates.
Running a Design Example
The steps for running each design example are identical. Simply substitute the name
of your preferred example from
Table 6–1 . For purposes of illustration, the steps in
this chapter refer to the alt_interlaken_8lane_6g design example.
This section describes the following steps for running the alt_interlaken_8lane_6g
design example:
1. Setting Up the Design Example
2. Creating the Quartus II Project and Generating the Qsys System
3. Simulating the System
4. Compiling and Programming the Device
Appendix C, Closing Timing on 10- and 20-lane Designs includes additional steps you
must follow to ensure that the alt_interlaken_20lane_6g design example achieves
timing closure on a Stratix IV GX FPGA.