Altera DQ (ALTDQ) - Manual (Page 9)

Getting Started Page 9
November 2010 Altera Corporation DQ (ALTDQ) and DQS (ALTDQS) Megafunctions
Page 5 of the ALTDQS parameter editor is the Output Registers page. Table 4 on
page 9 describes options available on page 5 of the ALTDQS megafunction.
Table 4. Output Register Settings
Option Description
Supported Devices
Cy
clone
II
Cyclone
III, Cyclone
IV
GX
Str
a
tix, St
ratix GX,
Stra
tix
II,
Stratix
II
GX, Arria
GX, HardCopy
II
What effect should the ‘dqs_areset’ port
have on output registers?
Use the dqs_areset port to asynchronously
preset or clear output registers. If you select the
None option, the signal is not instantiated and
you can specify the power-up state of the output
registers
Yes Yes Yes Yes
What effect should the ‘dqs_sreset’ port
have on output registers?
(1)
Use the dqs_sreset port to synchronously
preset or clear output registers. If you select the
None option, the port is not instantiated.
(2)
Yes Yes Yes Yes
How should the output registers power-
up?
(1)
If you selected None for the What effect should
the ‘dqs_areset’ port have on output
registers? option, use this option to specify
power-up condition of output registers.
Yes Yes Yes Yes
Use clock enable for the output register
(3)
Create the outclkena port (if not implemented
for the output registers). Use as a clock enable
for the output registers.
Yes Yes Yes Yes
Notes to Table 4 :
(1) Cyclone II devices do not support this feature. Option is disabled when Cyclone II device family is selected.
(2) This option is not available for Stratix II devices if the Allow DQS to be disabled during read postamble option has been selected on a previous
page of the wizard (refer to Table 3 on page 7 ).
(3) This option is enabled only when Register the output enable option is turned on in page 3 of the MegaWizard Plug-In Manager.