Altera DQ (ALTDQ) User Manual
Page 10
Page 10
Getting Started
DQ (ALTDQ) and DQS (ALTDQS) Megafunctions
November 2010
Altera Corporation
Page 6 of the ALTDQS parameter editor is the Output Enable Registers page.
describes options available on page 6 of the ALTDQS megafunction.
Table 5. Output Enable Registers Settings
Option
Description
Supported Devices
Cy
clone
II
Cyclone
III, Cyclone
IV
GX
Str
a
tix, St
ratix GX,
Stra
tix
II,
Stratix
II
GX, Arria
GX, HardCopy
II
What effect should the ‘dqs_areset’
port have on output enable registers?
Use the dqs_areset port to asynchronously
Preset or Clear the output-enable registers. If set
to None, the port is not instantiated and you have
the option to specify the power-up state of output
enable registers.
Yes
Yes
Yes
Yes
What effect should the ‘dqs_sreset’ port
have on output enable registers?
Use the dqs_areset port to synchronously
Preset or Clear output enable registers. If set to
None, the dqs_areset port is not instantiated.
Yes
Yes
Yes
Yes
How should the output enable registers
power-up?
If None is selected for the What effect should the
‘dqs_areset’ port have on output enable
registers?option, use this option to specify
power-up condition of output-enable registers.
Yes
Yes
Yes
Yes
Hold output drive at high impedance for
an extra half-clock cycle when output
enable goes high
Delays DQS write mode by half a clock cycle. The
DQS transitions from Z to 0, providing a cleaner
start to sequence than a Z to 1 transition.
Yes
Yes
Yes
Yes
Use clock enable for the output enable
register
Creates the outclkena port (if not implemented
for output enable register). Use as a clock-enable
for output enable register.
Yes
Yes
Yes
Yes
Notes to
:
(1) Cyclone II devices do not support this feature. Option is disabled when Cyclone II device family is selected.
(2) This option is not available for Stratix II devices if the Allow DQS to be disabled during read post-amble option has been selected on a previous
page of the MegaWizard Plug-In Manager (refer to