Altera DQ (ALTDQ) - Manual (Page 22)

Page 22 Specifications
DQ (ALTDQ) and DQS (ALTDQS) Megafunctions November 2010 Altera Corporation
ALTDQS
module altdqs
#(
parameter delay_buffer_mode = "low",
parameter delay_chain_mode = "static",
parameter intended_device_family = "unused",
parameter dll_delay_chain_length = 12,
parameter dll_delayctrl_mode = "normal",
parameter dll_jitter_reduction = "true",
parameter dll_offsetctrl_mode = "none",
parameter dll_phase_shift = "unused",
parameter dll_static_offset = "0",
parameter dll_use_reset = "false",
parameter dll_use_upndnin = "false",
parameter dll_use_upndninclkena = "false",
parameter dqs_ctrl_latches_enable = "true",
parameter dqs_delay_chain_length = 3,
parameter dqs_delay_chain_setting = "0",
parameter dqs_delay_requirement = "unused",
parameter dqs_edge_detect_enable = "false",
parameter dqs_oe_async_reset = "none",
parameter dqs_oe_power_up = "low",
parameter dqs_oe_register_mode = "register",
parameter dqs_oe_sync_reset = "none",
parameter dqs_open_drain_output = "false",
parameter dqs_output_async_reset = "none",
parameter dqs_output_power_up = "low",
parameter dqs_output_sync_reset = "none",
parameter dqs_use_dedicated_delayctrlin = "true",
parameter dqsn_mode = "none",
parameter extend_oe_disable = "true",
parameter gated_dqs = "false",
parameter has_dqs_delay_requirement = "true",
parameter input_frequency = "unused",
parameter invert_output = "false",
parameter number_of_dqs = 1,
parameter number_of_dqs_controls = 1,
parameter sim_invalid_lock = 100000,
parameter sim_valid_lock = 1,
parameter tie_off_dqs_oe_clock_enable = "false",
parameter tie_off_dqs_output_clock_enable = "false",
parameter lpm_type = "altdqs",
parameter lpm_hint = "unused")
( input wire dll_addnsub,
output wire [5:0] dll_delayctrlout,
input wire [5:0] dll_offset,
input wire dll_reset,
input wire dll_upndnin,
input wire dll_upndninclkena,
output wire dll_upndnout,
output wire [number_of_dqs-1:0] dqddioinclk,
output wire [number_of_dqs-1:0] dqinclk,
input wire [number_of_dqs_controls-1:0] dqs_areset,
input wire [number_of_dqs-1:0] dqs_datain_h,
input wire [number_of_dqs-1:0] dqs_datain_l,
input wire [5:0] dqs_delayctrlin,
inout wire [number_of_dqs-1:0] dqs_padio,
input wire [number_of_dqs_controls-1:0] dqs_sreset,
inout wire [number_of_dqs-1:0] dqsn_padio,
output wire [number_of_dqs-1:0] dqsundelayedout,
input wire [number_of_dqs-1:0] enable_dqs,
input wire inclk,
input wire [number_of_dqs_controls-1:0] oe,
input wire [number_of_dqs_controls-1:0] outclk,
input wire [number_of_dqs_controls-1:0] outclkena)/* synthesis syn_black_box=1 */;
endmodule //altdqs