Altera DQ (ALTDQ) - Manual (Page 27)

Ports and Parameters Page 27
November 2010 Altera Corporation DQ (ALTDQ) and DQS (ALTDQS) Megafunctions
Table 16 shows the input ports for the ALTDQS megafunction.
Table 17 shows the output ports for the ALTDQS megafunction.
Table 16. ALTDQS Megafunction Input Ports
Port Name Required Description
dqs_areset No Asynchronous set or reset signal for DQS output and output enable registers.
dqs_datain_h[] Yes
Data input port for DQS output register which outputs on rising edge of
outclk
signal.The size of the input port is dependent on the NUMBER_OF_DQS
parameter.
dqs_datain_l[] Yes
Data input port for DQS output register which outputs on falling edge of
outclk
signal. The size of the input port is dependent on the NUMBER_OF_DQS
parameter.
dqs_sreset No Synchronous set or reset signal for DQS output and output-enable registers.
inclk Yes System reference clock port that drives DLL.
oe No
Output enable for DQS output registers. When enabled, the oe port defaults to
V
CC
.
outclk Yes Clock to DQS output and output-enable registers.
outclkena No
Clock enable port for DQS output and oe registers. The oe port defaults to V
CC
when enabled.
dll_addnsub No
Bus for DLL delay setting offset that adds or subtracts. If omitted, value is
GND
. (1)
dll_upndnin No Data input for DLL delay setting offset. If omitted, value is GND. (1)
dll_offset[] No
Data input for DLL delay setting offset. The width of the input port is 6-bit
wide. If omitted, value is GND.
(1)
dqs_delayctrlin[] No
Control input to DQS delay buffers. The width of the input port is 6-bit wide. If
omitted, value is GND.
(1)
dll_upndninclkena No Clock enable for DLL delay setting offset. If omitted, value is GND. (1)
enable_dqs No
Specifies whether DQS is disabled during post-amble read. The enable_dqs
port is only available if the GATED_DQS parameter is specified to TRUE.
(2)
Notes to Table 16 :
(1) Available for Stratix II devices only.
(2) Available for Cyclone II devices only.
Table 17. ALTDQS Megafunction Output Ports (Part 1 of 2)
Port Name Required Description
dqinclk[] Yes
Phase shifted DQS strobe generated for DQ input registers from the DQS input.
Width of bus is equal to number of DQS pins. The size of the output port is
dependent on the NUMBER_OF_DQS parameter.
dll_delayctrlout[] No
Delay buffer setting output.If omitted, the default value is GND. The width of
the output port is 6-bit wide.
(1)
dll_upndnout No Output for DLL phase comparator. (1)
dqddioinclk[] No
Clocks generated for DQ negative-edge input registers from DQSn pins. The
width of the bus is equal to the number of DQS pins. The size of the output
port is dependent on the NUMBER_OF_DQS parameter.
(1)