Altera DQ (ALTDQ) - Manual (Page 21)

Specifications Page 21
November 2010 Altera Corporation DQ (ALTDQ) and DQS (ALTDQS) Megafunctions
Specifications
This section describes the prototypes, component declarations, ports, and parameters
of the ALTDQ and ALTDQS megafinctions. These ports and parameters are available
to customize the ALTDQ and ALTDQS megafunctions according to your application.
Verilog HDL Prototype
You can locate the following Verilog HDL prototypes in the Verilog Design File (.v)
altera_mf.v
in the <Quartus II installation directory>\eda\synthesis directory.
ALTDQ
module altdq
#(
parameter ddioinclk_input = "NEGATED_INCLK",
parameter intended_device_family = "unused",
parameter extend_oe_disable = "OFF",
parameter invert_input_clocks = "ON",
parameter number_of_dq = 1,
parameter oe_reg = "UNREGISTERED",
parameter power_up_high = "OFF",
parameter lpm_type = "altdq",
parameter lpm_hint = "unused")
( input wire aclr,
input wire aset,
input wire [number_of_dq-1:0] datain_h,
input wire [number_of_dq-1:0] datain_l,
output wire [number_of_dq-1:0] dataout_h,
output wire [number_of_dq-1:0] dataout_l,
input wire ddioinclk,
input wire inclock,
input wire inclocken,
input wire oe,
input wire outclock,
input wire outclocken,
inout wire [number_of_dq-1:0] padio)/* synthesis syn_black_box=1 */;
endmodule //altdq