Altera DQ (ALTDQ) - Manual (Page 16)

Page 16 Design Example: Implement DDR I/O Interface
DQ (ALTDQ) and DQS (ALTDQS) Megafunctions November 2010 Altera Corporation
Table 10 shows the MegaWizard Plug-In Manager page options and description you
should select to create the example ALTDQS megafunction.
Page 4 of the MegaWizard Plug-In Manager allows you to specify options for
stimulation and timing and resource estimation. This page normally lists the
simulation libraries required for functional simulation by third-party tools. However,
the ALTDQS megafunction does not have simulation model files, and cannot be
simulated.
Page 5 of the MegaWizard Plug-In Manager allows you to specify the generated file
types. The Variation file contains wrapper code in the HDL you specified on page 2a.
You can optionally generate Pin Planner ports PPF file (.ppf), AHDL Include file
(.inc), VHDL component declaration file (.cmp),
Quartus II symbol file (.bsf), Instantiation template file
(.v), and Verilog HDL black box file (_syn.v) is also
available. A gray check marks indicate files that are always generated; the other files
are optional and are generated only if selected (indicated by a red check mark). Turn
on the boxes to select the files that you want the wizard to generate. Perform these
steps to continue creating an ALTDQ megafunction:
1. Turn on the Instantiation template file and Verilog 'Black Box' declaration file
options.
2. Turn off the AHDL Include file, VHDL Component declaration file, and Quartus
symbol file options.
3. Click Finish.
Table 10. Parameter Settings for ALTDQ Megafunction
Page Option Description
1 Which action do you want to perform? Select Create a new custom megafunction variation
2a
Select a megafunction from the list
below
Select ALTDQ from the I/O category
Which device family will you be
using?
Select Cyclone II
Which type of output file do you want
to create?
Select Verilog HDL
What name do you want for the output
file? Browse to the folder dq_dqs_ex_1.0_restored. Name the file dq.
(If asked if it is okay to overwrite an existing file, click OK)
3
How many DQ pins would you like? Select 8
Which asynchronous reset port would
you like?
Select Asynchronous clear (aclr)
Create a clock enable port for each
clock port
Turn off option
Create an output enable port Turn on option
Register output enable Turn off option
Delay switch-on by a half clock cycle Turn off option
Invert input clock Turn off option
Use ‘ddioinclk’ port (from DQSn bus) Turn off option