Altera DQ (ALTDQ) - Manual (Page 3)

Getting Started Page 3
November 2010 Altera Corporation DQ (ALTDQ) and DQS (ALTDQS) Megafunctions
Common Applications
The ALTDQ and ALTDQS megafunctions implement proprietary interfaces and
variations of the external memories that require features not supported by the Altera
SDRAM controller and external memory interfaces.
1
You should use the clear-text data path generated by the DDR SDRAM Controller to
implement all DDR SDRAM, DDR2 SDRAM, RLDRAM II, and QDRII systems. This
data path has been validated by Altera and you can generate this data path for many
variations of these interfaces. To use the clear text data path, you need not purchase or
instantiate the Altera DDR SDRAM controller IP.
f For more information, refer to the DDR & DDR2 SDRAM Controller Compiler User
Guide , RLDRAM II Controller MegaCore Function User Guide , and QDRII SRAM
Controller MegaCore Function User Guide .
Resource Utilization and Performance
f For details about the resource utilization and performance of ALTDQ and ALTDQS
megafunctions, refer to the MegaWizard Plug-In Manager and the compilation
reports for each device in the Quartus II software.
Getting Started
f
The instructions in this section require the Quartus II software version 9.1 or later. For
operating system support information, refer to the
Operation System Support page on
the Altera website.
MegaWizard Plug-In Manager Page Option and Description for ALTDQS
Megafunction
Table 1 defines the parameterization options that are available in the MegaWizard
Plug-In Manager for the ALTDQS megafunction.
Table 1. MegaWizard Plug-In Manager Page Option and Description
Page Option Description
1
Which action do you want to
perform?
You can select from the following options: Create a new custom
megafunction variation, Edit an existing custom megafunction
variation, or Copy an existing custom megafunction variation.
2a
Select a megafunction from the list
below
Select ALTDQS from the I/O category.
Which device family will you be
using?
Specify the device family you want to use.
Which type of output file do you want
to create? You can choose from AHDL (.tdf), VHDL (.vhd), or Verilog HDL
(.v) as the output file type.
What name do you want for the
output file?
Specify the file name without the file extension.