Altera DQ (ALTDQ) - Manual (Page 8)

Page 8 Getting Started
DQ (ALTDQ) and DQS (ALTDQS) Megafunctions November 2010 Altera Corporation
How many valid half cycles of the
inclk input should pass before the
DLL simulates a lock?
Only affects simulation and has no affect on actual
device operation. Use to reduce number of clock
cycles for which a simulation must be run before the
DLL locks. By setting this to 1, the DLL immediately
locks and simulation can begin transferring data.
No No Yes Yes
How many invalid half clock cycles
of the inclk input should pass
before the DLL simulates a loss of
lock?
(2)
Only affects simulation and has no affect on actual
device operation. Use to reduce number of clock
cycles for which a simulation must be run before the
DLL locks. By setting this to 1, the DLL immediately
locks and simulation can begin transferring data.
No No Yes Yes
Notes to Table 3 :
(1) Low/high refers to jitter mode. The DLL in Stratix II device DQS phase-shift circuitry can operate between 100 and 300 MHz in either fast lock
mode or low jitter mode. Fast lock mode requires fewer clock cycles to calculate the input clock period, but the low jitter mode is more accurate.
The DQS delay settings (the up/down counter output) are updated every eight clock cycles. If the low jitter mode is enabled, the phase
comparator also issues a clock-enable signal to the up/down counter notifying the counter when to update the DQS settings. In low jitter mode,
the enable signal is only active when the upndn signal is incremented or decremented by 4, otherwise the clock-enable is off and the DQS delay
settings do not get updated. This enable signal is always active if the DLL is in fast lock mode.
(2) Stratix II devices do not support this feature, and the option is disabled in the MegaWizard Plug-In Manager for these devices.
Table 3. General 2 Settings (Part 2 of 2)
Option Description
Supported Devices
Cyclon
e
II
Cyc
lone
III, C
yclone
IV
GX
St
ratix, Strat
ix GX,
Stratix
II, Stratix
II
GX,
Arria
GX,
Ha
rdCopy
II