Pilz PNOZ mmc1p ETH - Manual (Page 33)

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3.4 Assignment of data areas
3 Modbus/TCP - Data areas
3.4.11 State of process data
State of process data 3- ModbusTCP_Datenbereiche-Zustand der Prozessdaten
The table below describes the Modbus/TCP data areas that contain the
status info register. The general state of the data is reproduced in the
status info register.
Relevant areas for the data are defined in the Modbus/TCP data areas
Discrete Inputs (1x) and Input Register (3x). Read access is available to
these data areas.
Bit 5 "WD Timeout": The set watchdog for the input bits has been trig-
gered and the inputs set to "0".
Bit 0 "Error Bit": The content of the data areas is not current or the set
watchdog for the input bits has been triggered.
Register
(3x) Coil/
Discrete Input
(1x) Content High Byte Low Byte
2048 32783... 32768 Status information See below
High Byte Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Low Byte Reserved Reserved WD Time-
out Reserved Reserved Reserved Reserved Global Er-
ror Bit