Echelon LonTal Stack - Manual (Page 44)

32 Designing the Serial I/O Hardware Interface
Overview of the Hardware Interface
This chapter describes the hardware interface, including the requirement for
pull-up resistors, selecting a minimum communications interface bit rate,
considerations for host latency, specifying the SCI interface, and how to perform
an initial health check of the Echelon Smart Transceiver.
Reliability
The LonTalk Stack link layer protocol assumes a reliable serial link and does not
include error detection or error recovery. Instead, error detection and recovery
are implemented by the LonTalk protocol, and this protocol detects and recovers
from errors.
To minimize possible link-layer errors, be sure to design the hardware interface
for reliable and robust operations. For example, use a star-ground configuration
for your device layout on the device’s printed circuit board (PCB), limit entry
points for electrostatic discharge (ESD) current, provide ground guarding for
switching power supply control loops, provide good decoupling for V
DD
inputs, and
maintain separation between digital circuitry and cabling for the network and
power. See the FT 3120 / FT 3150 Echelon Smart Transceiver Data Book, the PL
3120 / PL 3150 / PL 3170 Power Line Echelon Smart Transceiver Data Book, or
the Series 5000 Chip Data Book for more information about PCB design
considerations for an Echelon Smart Transceiver.
The example applications contain example implementations of the link layer
driver, including examples and recommendations for time-out guards within the
various states of that driver.
Serial Communication Lines
For the SCI serial interfaces, you must add 10 k Ω pull-up resistors to the two
communication lines between the host processor and the Echelon Smart
Transceiver or Neuron Chip. These pull-up resistors prevent invalid transactions
on start-up and reset of the host processor or the Echelon Smart Transceiver or
Neuron Chip. Without a pull-up resistor, certain I/O pins can revert to a floating
state during start-up, which can cause unpredictable results.
High-speed communication lines should also include proper back termination.
Place a series resistor with a value equal to the characteristic impedance (Z
0
) of
the PCB trace minus the output impedance of the driving gate (the resistor value
should be approximately 50 Ω) at the driving pin. In addition, the trace should
run on the top layer of the PCB, over the inner ground plane, and should not
have any vias to the other side of the PCB. Low-impedance routing and correct
line termination is increasingly important with higher link layer bit rates, so
carefully check the signal quality for both the Echelon Smart Transceiver or
Neuron Chip and the host when you design and test new LonTalk Stack device
hardware, or when you change the link-layer parameters for existing LonTalk
Stack device hardware.