Echelon FTXL Hardware - Manual (Page 90)

82 Index
headers, 16
jumpers, 16
LEDs, 16
overview, 15
H
HAL, 50
handshaking, 23
hardware abstraction layer, 50
hardware interface
control signal buffer, 20
data bus isolation, 20
DC-DC converter, 20
overview, 20
pull-up resistors, 21
hardware, overview, 2
headers
DBC2C20 development board, 11
FTXL Adapter Board, 13
FTXL Transceiver Board, 16
host receive, control flow, 29
host send, control flow, 32
HS pin, 22
I
I/O pins, 24
interface. See parallel communications
interface, See hardware interface
interrupt test, bring-up application, 78
interrupt, bring-up application, 68
IO0-IO10 pins, 24
IRQ pin, 24
IRQ requirements, 49
J
jumpers
DBC2C20 development board, 11
FTXL Adapter Board, 13
FTXL Transceiver Board, 16
L
LEDs
DBC2C20 development board, 9
FTXL Transceiver Board, 16
loading, application image, 62
LVI, reset, 27
M
MegaCore IP library, 54
memory, external, 48
ModelSim simulation tool, 54
modifying the design
Quartus II, 60
SOPC Builder, 57
N
Nios II Embedded Design Suite, 54
Nios II processor, 40
P
parallel communications interface
handshake, 23
overview, 21
pin assignments, 21
token passing, 23
transferring data, 23
parallel I/O transceiver interface, 43
parallel interface delay, 42
phase-locked loop, 48
pins
A0, 22
assignments, 21, 28
characteristics, 24
clock, 27
CS~, 22
D0-D7, 22
FPGA, 28
HS, 22
I/O, 24
IRQ, 24
R/W~, 22
RESET~, 25
service, 27
PLL, 48
power-up sequence, 26
pull-up resistors, 21
Q
Quartus II software, 54
R
R/W~ pin, 22
reference design, 38
reset
bring-up application, 65
LVI, 27
overview, 25
power-up sequence, 26
software controlled, 27
timing, 27
watchdog timer, 27
reset test, bring-up application, 71
RESET~ pin, 25
S
search paths, 56
service LED, 46
service pin, 27, 47
service pin test, bring-up application, 79