Echelon FTXL Hardware - Manual (Page 89)

FTXL Hardware Guide 81
Index
A
A0 pin, 22
addressing requirements, 49
Altera Complete Design Suite, 54
application image
building, 61
loading, 62
B
bring-up application
additional tests, 80
building, 70
data register, 66
framework, 64
interface, 65
interrupt, 68
interrupt functions, 64
new project, 69
Nios IDE, 69
overview, 64
reset signal, 65
running, 70
status signals, 66
tests, 70
building, application image, 61
buttons, DBC2C20 development board, 9
C
clock pins, 27
communications lines, pull-ups, 21
components
adding, 57
DBC2C20, 48
FTXL, 41
requirements, 49
search paths, 56
configuration device, FPGA, 40
connectors
DBC2C20 development board, 11
FTXL Adapter Board, 13
FTXL Transceiver Board, 16
control flow
host from FTXL Transceiver, 32
host to FTXL Transceiver, 29
control signal buffer, 20
CS~ pin, 22
D
D0-D7 pins, 22
data bus isolation, 20
data register, bring-up application, 66
data transfer, 23
data-passing test, bring-up application, 76
DBC2C20 development board
buttons, 9
components, 48
connectors, 11
headers, 11
jumpers, 11
LEDs, 9
overview, 8
DC-DC converter, 20
design, modifying, 57, 60
devboards.de GmbH, 3
developer's kit.
See FTXL Developer's Kit
development process
FPGA design, 5
hardware design, 4
overview, 3
software design, 5
development tools, 54
device programmer, 55
documentation
Altera, iv
devboards, v
Echelon, iii
downlink control flow, 32
E
EBV Elektronik GmbH, 3
external memory, 48
F
FPGA
configuration device, 40
design, 38
device requirements, 39
FTXL Adapter Board
connectors, 13
headers, 13
jumpers, 13
overview, 13
FTXL Developer's Kit
components, 41
DBC2C20 development board, 8
hardware, 8
overview, 3
reference design, 38
FTXL Transceiver Board
connectors, 16