Echelon FTXL Hardware - Manual (Page 28)

20 FTXL Transceiver Hardware Interface
Overview of the Hardware Interface
The hardware interface for an FTXL Transceiver is comprised of the parallel
communications interface, the pin assignments and characteristics for the FTXL
Transceiver Chip, and the pin assignments and characteristics for the FPGA
device. This chapter describes the hardware interface.
The FTXL 3190 Free Topology Smart Transceiver shares electrical and physical
characteristics with the FT 3120 Smart Transceiver. For information about the
hardware interface for an FT 3120 Smart Transceiver, see the FT 3120 / FT 3150
Smart Transceiver Data Book .
DC-DC Converter
Because the Cyclone II FPGA requires 3.3 V input voltage, and the FTXL
Transceiver Chip requires 5 V input voltage, your hardware design must include
either a separate power supply for each of the two parts, or a DC-DC step-up or
step-down converter chip with a common power supply for both parts.
Important: The Cyclone II FPGA pins are not 5V-tolerant.
The FTXL Developer’s Kit reference design uses the power supply on the
DBC2C20 development board, and the FTXL Adapter Board uses a Texas
Instruments™ TPS60110 step-up, regulated charge pump DC-DC converter to
provide the necessary 5 V for the FTXL Transceiver Chip from the DBC2C20
development board’s 3.3 V power supply.
Control Signal Buffer
For an FPGA device that does not have 5V-tolerant input pins, you need to buffer
the control signals between the FTXL Transceiver and the FPGA device. The
control signals are the CS~, R/W~, A0, IRQ, and RESET~ signals described in
The Parallel Communications Interface on page 21.
The FTXL Adapter Board uses an NXP ® Semiconductor 74AHC541 three-state
octal buffer/line driver to provide buffering for the FTXL control signals.
The FTXL RESET~ signal also requires an additional 100 Ω resistor in-series
between the FTXL Transceiver and the buffer/line driver device. See the
FT
3120 / FT 3150 Smart Transceiver Data Book for other considerations for the
RESET~ signal, such as providing a comparator circuit that can monitor when
the power-supply voltage goes out of tolerance.
Data Bus Isolation
For an FPGA device that does not have 5V-tolerant input pins, you need to
provide isolation for the data bus signals between the FTXL Transceiver and the
FPGA device. The data bus signals are the D0..D7 signals described in The
Parallel Communications Interface on page 21.
The FTXL Adapter Board uses an NXP Semiconductor 74AHC245 three-state
octal bus transceiver to provide signal isolation for the FTXL data bus.